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git01.mediatek.com / filogic / uboot / c2a441cbbe85d81d5104a349bb8fadd8879348c3 / . / board / zyxel / nsa325 / nsa325.c
blob: 38340b33c8bf5bccb5ed60b5d42b97e17cdd8056 [file] [log] [blame]
Tony Dinhc0f94df2023-08-25 20:33:29 -0700[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2014-2023 Tony Dinh <mibodhi@gmail.com>
4 *
5 * Based on
6 * Copyright (C) 2014 Jason Plum <jplum@archlinuxarm.org>
7 *
8 * Based on nsa320.c originall written by
9 * Copyright (C) 2012 Peter Schildmann <linux@schildmann.info>
10 *
11 * Based on guruplug.c originally written by
12 * Siddarth Gore <gores@marvell.com>
13 * (C) Copyright 2009
14 * Marvell Semiconductor <www.marvell.com>
15 */
16
Tony Dinhc0f94df2023-08-25 20:33:29 -0700[diff] [blame]17#include <asm/arch/soc.h>
18#include <asm/arch/mpp.h>
19#include <netdev.h>
20#include <asm/arch/cpu.h>
21#include <asm/gpio.h>
22#include <asm/io.h>
23#include <asm/arch/gpio.h>
24#include <asm/mach-types.h>
25#include <bootstage.h>
26#include <command.h>
27#include <init.h>
28#include <linux/bitops.h>
29
30DECLARE_GLOBAL_DATA_PTR;
31
32/* low GPIO's */
33#define HDD2_GREEN_LED BIT(12)
34#define HDD2_RED_LED BIT(13)
35#define USB_GREEN_LED BIT(15)
36#define USB_POWER BIT(21)
37#define SYS_GREEN_LED BIT(28)
38#define SYS_ORANGE_LED BIT(29)
39
40#define PIN_USB_GREEN_LED 15
41#define PIN_USB_POWER 21
42
43#define NSA325_OE_LOW (~(HDD2_GREEN_LED | HDD2_RED_LED | \
44 USB_GREEN_LED | USB_POWER | \
45 SYS_GREEN_LED | SYS_ORANGE_LED))
46#define NSA325_VAL_LOW (SYS_GREEN_LED | USB_POWER)
47
48/* high GPIO's */
49#define COPY_GREEN_LED BIT(7)
50#define COPY_RED_LED BIT(8)
51#define HDD1_GREEN_LED BIT(9)
52#define HDD1_RED_LED BIT(10)
53#define HDD2_POWER BIT(15)
54#define WATCHDOG_SIGNAL BIT(14)
55
56#define NSA325_OE_HIGH (~(COPY_GREEN_LED | COPY_RED_LED | \
57 HDD1_GREEN_LED | HDD1_RED_LED | HDD2_POWER | WATCHDOG_SIGNAL))
58#define NSA325_VAL_HIGH (WATCHDOG_SIGNAL | HDD2_POWER)
59
60#define BTN_POWER 46
61#define BTN_RESET 36
62#define BTN_COPY 37
63
64int board_early_init_f(void)
65{
66 /*
67 * default gpio configuration
68 * There are maximum 64 gpios controlled through 2 sets of registers
69 * the below configuration configures mainly initial LED status
70 */
71 mvebu_config_gpio(NSA325_VAL_LOW, NSA325_VAL_HIGH,
72 NSA325_OE_LOW, NSA325_OE_HIGH);
73
74 /* Multi-Purpose Pins Functionality configuration */
75 /* (all LEDs & power off active high) */
76 u32 kwmpp_config[] = {
77 MPP0_NF_IO2,
78 MPP1_NF_IO3,
79 MPP2_NF_IO4,
80 MPP3_NF_IO5,
81 MPP4_NF_IO6,
82 MPP5_NF_IO7,
83 MPP6_SYSRST_OUTn,
84 MPP7_GPO,
85 MPP8_TW_SDA, /* PCF8563 RTC chip */
86 MPP9_TW_SCK, /* connected to TWSI */
87 MPP10_UART0_TXD,
88 MPP11_UART0_RXD,
89 MPP12_GPO, /* HDD2 LED (green) */
90 MPP13_GPIO, /* HDD2 LED (red) */
91 MPP14_GPIO, /* MCU DATA pin (in) */
92 MPP15_GPIO, /* USB LED (green) */
93 MPP16_GPIO, /* MCU CLK pin (out) */
94 MPP17_GPIO, /* MCU ACT pin (out) */
95 MPP18_NF_IO0,
96 MPP19_NF_IO1,
97 MPP20_GPIO,
98 MPP21_GPIO, /* USB power */
99 MPP22_GPIO,
100 MPP23_GPIO,
101 MPP24_GPIO,
102 MPP25_GPIO,
103 MPP26_GPIO,
104 MPP27_GPIO,
105 MPP28_GPIO, /* SYS LED (green) */
106 MPP29_GPIO, /* SYS LED (orange) */
107 MPP30_GPIO,
108 MPP31_GPIO,
109 MPP32_GPIO,
110 MPP33_GPIO,
111 MPP34_GPIO,
112 MPP35_GPIO,
113 MPP36_GPIO, /* reset button */
114 MPP37_GPIO, /* copy button */
115 MPP38_GPIO, /* VID B0 */
116 MPP39_GPIO, /* COPY LED (green) */
117 MPP40_GPIO, /* COPY LED (red) */
118 MPP41_GPIO, /* HDD1 LED (green) */
119 MPP42_GPIO, /* HDD1 LED (red) */
120 MPP43_GPIO, /* HTP pin */
121 MPP44_GPIO, /* buzzer */
122 MPP45_GPIO, /* VID B1 */
123 MPP46_GPIO, /* power button */
124 MPP47_GPIO, /* HDD2 power */
125 MPP48_GPIO, /* power off */
126 0
127 };
128 kirkwood_mpp_conf(kwmpp_config, NULL);
129 return 0;
130}
131
132int board_eth_init(struct bd_info *bis)
133{
134 return cpu_eth_init(bis);
135}
136
137int board_init(void)
138{
139 /* address of boot parameters */
140 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
141
142 return 0;
143}
144
145int board_late_init(void)
146{
147 /* Do late init to ensure successful enumeration of XHCI devices */
148 pci_init();
149 return 0;
150}
151
152#if defined(CONFIG_SHOW_BOOT_PROGRESS)
153void show_boot_progress(int val)
154{
155 struct kwgpio_registers *gpio0 = (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
156 u32 dout0 = readl(&gpio0->dout);
157 u32 blen0 = readl(&gpio0->blink_en);
158
159 struct kwgpio_registers *gpio1 = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
160 u32 dout1 = readl(&gpio1->dout);
161 u32 blen1 = readl(&gpio1->blink_en);
162
163 switch (val) {
164 case BOOTSTAGE_ID_DECOMP_IMAGE:
165 writel(blen0 & ~(SYS_GREEN_LED | SYS_ORANGE_LED), &gpio0->blink_en);
166 writel((dout0 & ~SYS_GREEN_LED) | SYS_ORANGE_LED, &gpio0->dout);
167 break;
168 case BOOTSTAGE_ID_RUN_OS:
169 writel(dout0 & ~SYS_ORANGE_LED, &gpio0->dout);
170 writel(blen0 | SYS_GREEN_LED, &gpio0->blink_en);
171 break;
172 case BOOTSTAGE_ID_NET_START:
173 writel(dout1 & ~COPY_RED_LED, &gpio1->dout);
174 writel((blen1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->blink_en);
175 break;
176 case BOOTSTAGE_ID_NET_LOADED:
177 writel(blen1 & ~(COPY_RED_LED | COPY_GREEN_LED), &gpio1->blink_en);
178 writel((dout1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->dout);
179 break;
180 case -BOOTSTAGE_ID_NET_NETLOOP_OK:
181 case -BOOTSTAGE_ID_NET_LOADED:
182 writel(dout1 & ~COPY_GREEN_LED, &gpio1->dout);
183 writel((blen1 & ~COPY_GREEN_LED) | COPY_RED_LED, &gpio1->blink_en);
184 break;
185 default:
186 if (val < 0) {
187 /* error */
188 printf("Error occurred, error code = %d\n", -val);
189 writel(dout0 & ~SYS_GREEN_LED, &gpio0->dout);
190 writel(blen0 | SYS_ORANGE_LED, &gpio0->blink_en);
191 }
192 break;
193 }
194}
195#endif /* CONFIG_SHOW_BOOT_PROGRESS */