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git01.mediatek.com / filogic / uboot / c2a441cbbe85d81d5104a349bb8fadd8879348c3 / . / arch / arm / dts / imx8mp-rsb3720-a1-u-boot.dtsi
blob: 21eff6d6ad4debb76d5d02fa1dd479beae59174a [file] [log] [blame]
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 NXP
4 * Copyright 2022 Linaro
5 */
6
7#include "imx8mp-u-boot.dtsi"
8
9/ {
10 wdt-reboot {
11 compatible = "wdt-reboot";
12 wdt = <&wdog1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]13 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]14 };
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]15};
16
17&iomuxc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]18 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]19};
20
21&reg_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]22 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]23};
24
25&pinctrl_uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]26 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]27};
28
29&pinctrl_uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]30 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]31};
32
33&pinctrl_usdhc2_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]34 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]35};
36
37&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]38 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]39};
40
41&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]42 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]43};
44
45&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]46 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]47};
48
49&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]50 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]51};
52
53&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]54 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]55};
56
57&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]58 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]59};
60
61&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]62 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]63};
64
65&uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]66 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]67};
68
69&uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]70 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]71};
72
73&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]74 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]75};
76
77&i2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]78 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]79};
80
81&i2c3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]82 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]83};
84
Peng Fanb00e4292022-06-11 20:21:08 +0800[diff] [blame]85&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]86 bootph-pre-ram;
Peng Fanb00e4292022-06-11 20:21:08 +0800[diff] [blame]87};
88
89&pinctrl_wdog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]90 bootph-pre-ram;
Peng Fanb00e4292022-06-11 20:21:08 +0800[diff] [blame]91};
92
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]93&pinctrl_i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]94 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]95};
96
97&pinctrl_i2c1_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]98 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]99};
100
101&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]102 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]103};
104
105&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]106 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]107};
108
109&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]110 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]111};
112
113&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]114 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]115 assigned-clocks = <&clk IMX8MP_CLK_USDHC1>;
116 assigned-clock-rates = <400000000>;
117 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
118};
119
120&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]121 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]122 sd-uhs-sdr104;
123 sd-uhs-ddr50;
124 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
125 assigned-clock-rates = <400000000>;
126 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
127};
128
129&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]130 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]131 mmc-hs400-1_8v;
132 mmc-hs400-enhanced-strobe;
133 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
134 assigned-clock-rates = <400000000>;
135 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
136};
137
Marek Vasut9fe526d2024-05-21 12:48:24 +0200[diff] [blame]138&binman_imx_fit {
139 images {
140 fip {
141 description = "Trusted Firmware FIP";
142 type = "firmware";
143 arch = "arm64";
144 compression = "none";
145 load = <0x40310000>;
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]146
Marek Vasut9fe526d2024-05-21 12:48:24 +0200[diff] [blame]147 fip_blob: blob-ext{
148 filename = "fip.bin";
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]149 };
Ying-Chun Liu (PaulLiu)f183f132022-01-26 20:33:02 +0800[diff] [blame]150 };
151 };
152};
Ying-Chun Liu (PaulLiu)7cccd052023-01-18 03:15:00 +0800[diff] [blame]153
Simon Glassceea7842023-08-23 19:18:01 -0600[diff] [blame]154/* This cannot work since it refers to a template node
Ying-Chun Liu (PaulLiu)7cccd052023-01-18 03:15:00 +0800[diff] [blame]155&binman_configuration {
156 loadables = "atf", "fip";
157};
Simon Glassceea7842023-08-23 19:18:01 -0600[diff] [blame]158*/