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git01.mediatek.com / filogic / uboot / c2a441cbbe85d81d5104a349bb8fadd8879348c3 / . / arch / arm / dts / imx8mp-dhcom-som-overlay-rev100.dts
blob: b2154d57e489e769c7f8c9f0b98df7a2f39e23a1 [file] [log] [blame]
Marek Vasuteaee3032023-09-21 20:44:20 +0200[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) 2023 Marek Vasut <marex@denx.de>
4 */
5/dts-v1/;
6/plugin/;
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10
11#include "imx8mp-pinfunc.h"
12
13&brcmf {
14 reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
15};
16
17&eeprom0 { /* EEPROM with EQoS MAC address */
18 compatible = "atmel,24c02";
19 pagesize = <16>;
20};
21
22&eeprom1 { /* EEPROM with FEC MAC address */
23 compatible = "atmel,24c02";
24 pagesize = <16>;
25};
26
Marek Vasut3d9a20d2023-10-16 02:05:25 +0200[diff] [blame]27&eeprom0wl {
28 status = "disabled";
29};
30
31&eeprom1wl {
32 status = "disabled";
33};
34
Marek Vasuteaee3032023-09-21 20:44:20 +0200[diff] [blame]35&ethphy0f { /* SMSC LAN8740Ai */
36 pinctrl-0 = <&pinctrl_ethphy0 &pinctrl_ioexp>;
37 reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
Marek Vasut78e24b42024-06-27 02:13:16 +0200[diff] [blame]38 reg = <0>;
Marek Vasuteaee3032023-09-21 20:44:20 +0200[diff] [blame]39};
40
41&ethphy0g { /* Micrel KSZ9131RNXI */
42 pinctrl-0 = <&pinctrl_ethphy0 &pinctrl_ioexp>;
43 reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
44};
45
Marek Vasut78e24b42024-06-27 02:13:16 +0200[diff] [blame]46&ethphy1f { /* SMSC LAN8740Ai */
47 reg = <1>;
48};
49
Marek Vasuteaee3032023-09-21 20:44:20 +0200[diff] [blame]50&i2c3 {
51 adc@48 {
52 compatible = "ti,tla2024";
53 interrupts-extended;
54 };
55};
56
57&ioexp {
58 status = "disabled";
59};
60
61&reg_eth_vio {
62 gpio = <&gpio2 10 GPIO_ACTIVE_LOW>;
63 pinctrl-0 = <&pinctrl_enet_vio>;
64 pinctrl-names = "default";
65};
66
67&rv3032 {
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_rtc>;
70 interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>;
71};
72
73&uart2 {
74 bluetooth {
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_uart2_bt>;
77 shutdown-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
78 };
79};
80
81&usb_dwc3_0 {
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_usb0_vbus>;
84};
85
86&usdhc1 {
87 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_wl_reg_en>;
88 pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_usdhc1_wl_reg_en>;
89 pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_usdhc1_wl_reg_en>;
90};
91
92&iomuxc {
93 pinctrl-0 = <&pinctrl_hog_base
94 &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
95 &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
96 &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
97 &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
98 /* GPIO_M is connected to CLKOUT2 */
99 &pinctrl_dhcom_int>;
100
101 pinctrl_enet_vio: dhcom-enet-vio-grp {
102 fsl,pins = <
103 MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x22
104 >;
105 };
106
107 pinctrl_rtc: dhcom-rtc-grp {
108 fsl,pins = <
109 /* RTC_#INT Interrupt */
110 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x400001c6
111 >;
112 };
113
114 pinctrl_uart2_bt: dhcom-uart2-bt-grp {
115 fsl,pins = <
116 /* BT_REG_EN */
117 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
118 >;
119 };
120
121 pinctrl_usb0_vbus: dhcom-usb0-grp {
122 fsl,pins = <
123 MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x0
124 >;
125 };
126
127 pinctrl_usdhc1_wl_reg_en: dhcom-usdhc1-wl-reg-en-grp {
128 fsl,pins = <
129 /* WL_REG_EN */
130 MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
131 >;
132 };
133};