wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2003 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
Wolfgang Denk | 34ca9d3 | 2005-09-25 18:49:35 +0200 | [diff] [blame] | 5 | * Copyright (c) 2005 MontaVista Software, Inc. |
Wolfgang Denk | 8cc89d9 | 2005-09-25 16:27:55 +0200 | [diff] [blame] | 6 | * Vitaly Bordug <vbordug@ru.mvista.com> |
| 7 | * Added support for PCI bridge on MPC8272ADS |
| 8 | * |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 9 | * See file CREDITS for list of people who contributed to this |
| 10 | * project. |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or |
| 13 | * modify it under the terms of the GNU General Public License as |
| 14 | * published by the Free Software Foundation; either version 2 of |
| 15 | * the License, or (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 25 | * MA 02111-1307 USA |
| 26 | */ |
| 27 | |
| 28 | #include <common.h> |
| 29 | |
| 30 | #ifdef CONFIG_PCI |
| 31 | |
| 32 | #include <pci.h> |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 33 | #include <mpc8260.h> |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 34 | #include <asm/m8260_pci.h> |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 35 | #include <asm/io.h> |
Matvejchikov Ilya | 8743c79 | 2008-07-06 13:57:00 +0400 | [diff] [blame] | 36 | #ifdef CONFIG_OF_LIBFDT |
| 37 | #include <libfdt.h> |
| 38 | #include <fdt_support.h> |
| 39 | #endif |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 40 | |
Wolfgang Denk | e5357d0 | 2006-05-30 23:32:44 +0200 | [diff] [blame] | 41 | #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826 |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 42 | DECLARE_GLOBAL_DATA_PTR; |
| 43 | #endif |
| 44 | |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 45 | /* |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 46 | * Local->PCI map (from CPU) controlled by |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 47 | * MPC826x master window |
| 48 | * |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 49 | * 0x80000000 - 0xBFFFFFFF CPU2PCI space PCIBR0 |
| 50 | * 0xF4000000 - 0xF7FFFFFF CPU2PCI space PCIBR1 |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 51 | * |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 52 | * 0x80000000 - 0x9FFFFFFF 0x80000000 - 0x9FFFFFFF (Outbound ATU #1) |
| 53 | * PCI Mem with prefetch |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 54 | * |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 55 | * 0xA0000000 - 0xBFFFFFFF 0xA0000000 - 0xBFFFFFFF (Outbound ATU #2) |
| 56 | * PCI Mem w/o prefetch |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 57 | * |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 58 | * 0xF4000000 - 0xF7FFFFFF 0x00000000 - 0x03FFFFFF (Outbound ATU #3) |
| 59 | * 32-bit PCI IO |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 60 | * |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 61 | * PCI->Local map (from PCI) |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 62 | * MPC826x slave window controlled by |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 63 | * |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 64 | * 0x00000000 - 0x1FFFFFFF 0x00000000 - 0x1FFFFFFF (Inbound ATU #1) |
| 65 | * MPC826x local memory |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 66 | */ |
| 67 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 68 | /* |
| 69 | * Slave window that allows PCI masters to access MPC826x local memory. |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 70 | * This window is set up using the first set of Inbound ATU registers |
| 71 | */ |
| 72 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 73 | #ifndef CFG_PCI_SLV_MEM_LOCAL |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 74 | #define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 75 | #else |
| 76 | #define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 77 | #endif |
| 78 | |
| 79 | #ifndef CFG_PCI_SLV_MEM_BUS |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 80 | #define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 81 | #else |
| 82 | #define PCI_SLV_MEM_BUS CFG_PCI_SLV_MEM_BUS |
| 83 | #endif |
| 84 | |
| 85 | #ifndef CFG_PICMR0_MASK_ATTRIB |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 86 | #define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 87 | PICMR_PREFETCH_EN) |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 88 | #else |
| 89 | #define PICMR0_MASK_ATTRIB CFG_PICMR0_MASK_ATTRIB |
| 90 | #endif |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 91 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 92 | /* |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 93 | * These are the windows that allow the CPU to access PCI address space. |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 94 | * All three PCI master windows, which allow the CPU to access PCI |
| 95 | * prefetch, non prefetch, and IO space (see below), must all fit within |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 96 | * these windows. |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 97 | */ |
| 98 | |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 99 | /* PCIBR0 */ |
| 100 | #ifndef CFG_PCI_MSTR0_LOCAL |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 101 | #define PCI_MSTR0_LOCAL 0x80000000 /* Local base */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 102 | #else |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 103 | #define PCI_MSTR0_LOCAL CFG_PCI_MSTR0_LOCAL |
| 104 | #endif |
| 105 | |
| 106 | #ifndef CFG_PCIMSK0_MASK |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 107 | #define PCIMSK0_MASK PCIMSK_1GB /* Size of window */ |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 108 | #else |
| 109 | #define PCIMSK0_MASK CFG_PCIMSK0_MASK |
| 110 | #endif |
| 111 | |
| 112 | /* PCIBR1 */ |
| 113 | #ifndef CFG_PCI_MSTR1_LOCAL |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 114 | #define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 115 | #else |
| 116 | #define PCI_MSTR1_LOCAL CFG_PCI_MSTR1_LOCAL |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 117 | #endif |
| 118 | |
| 119 | #ifndef CFG_PCIMSK1_MASK |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 120 | #define PCIMSK1_MASK PCIMSK_64MB /* Size of window */ |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 121 | #else |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 122 | #define PCIMSK1_MASK CFG_PCIMSK1_MASK |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 123 | #endif |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 124 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 125 | /* |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 126 | * Master window that allows the CPU to access PCI Memory (prefetch). |
| 127 | * This window will be setup with the first set of Outbound ATU registers |
| 128 | * in the bridge. |
| 129 | */ |
| 130 | |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 131 | #ifndef CFG_PCI_MSTR_MEM_LOCAL |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 132 | #define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 133 | #else |
| 134 | #define PCI_MSTR_MEM_LOCAL CFG_PCI_MSTR_MEM_LOCAL |
| 135 | #endif |
| 136 | |
| 137 | #ifndef CFG_PCI_MSTR_MEM_BUS |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 138 | #define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 139 | #else |
| 140 | #define PCI_MSTR_MEM_BUS CFG_PCI_MSTR_MEM_BUS |
| 141 | #endif |
| 142 | |
| 143 | #ifndef CFG_CPU_PCI_MEM_START |
| 144 | #define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL |
| 145 | #else |
| 146 | #define CPU_PCI_MEM_START CFG_CPU_PCI_MEM_START |
| 147 | #endif |
| 148 | |
| 149 | #ifndef CFG_PCI_MSTR_MEM_SIZE |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 150 | #define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */ |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 151 | #else |
| 152 | #define PCI_MSTR_MEM_SIZE CFG_PCI_MSTR_MEM_SIZE |
| 153 | #endif |
| 154 | |
| 155 | #ifndef CFG_POCMR0_MASK_ATTRIB |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 156 | #define POCMR0_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN) |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 157 | #else |
| 158 | #define POCMR0_MASK_ATTRIB CFG_POCMR0_MASK_ATTRIB |
| 159 | #endif |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 160 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 161 | /* |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 162 | * Master window that allows the CPU to access PCI Memory (non-prefetch). |
| 163 | * This window will be setup with the second set of Outbound ATU registers |
| 164 | * in the bridge. |
| 165 | */ |
| 166 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 167 | #ifndef CFG_PCI_MSTR_MEMIO_LOCAL |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 168 | #define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 169 | #else |
| 170 | #define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 171 | #endif |
| 172 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 173 | #ifndef CFG_PCI_MSTR_MEMIO_BUS |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 174 | #define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 175 | #else |
| 176 | #define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 177 | #endif |
| 178 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 179 | #ifndef CFG_CPU_PCI_MEMIO_START |
| 180 | #define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL |
| 181 | #else |
| 182 | #define CPU_PCI_MEMIO_START CFG_CPU_PCI_MEMIO_START |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 183 | #endif |
| 184 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 185 | #ifndef CFG_PCI_MSTR_MEMIO_SIZE |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 186 | #define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 187 | #else |
| 188 | #define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 189 | #endif |
| 190 | |
| 191 | #ifndef CFG_POCMR1_MASK_ATTRIB |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 192 | #define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 193 | #else |
| 194 | #define POCMR1_MASK_ATTRIB CFG_POCMR1_MASK_ATTRIB |
| 195 | #endif |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 196 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 197 | /* |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 198 | * Master window that allows the CPU to access PCI IO space. |
| 199 | * This window will be setup with the third set of Outbound ATU registers |
| 200 | * in the bridge. |
| 201 | */ |
| 202 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 203 | #ifndef CFG_PCI_MSTR_IO_LOCAL |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 204 | #define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 205 | #else |
| 206 | #define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 207 | #endif |
| 208 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 209 | #ifndef CFG_PCI_MSTR_IO_BUS |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 210 | #define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 211 | #else |
| 212 | #define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 213 | #endif |
| 214 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 215 | #ifndef CFG_CPU_PCI_IO_START |
| 216 | #define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL |
| 217 | #else |
| 218 | #define CPU_PCI_IO_START CFG_CPU_PCI_IO_START |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 219 | #endif |
| 220 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 221 | #ifndef CFG_PCI_MSTR_IO_SIZE |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 222 | #define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 223 | #else |
| 224 | #define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE |
wdenk | e5d61c7 | 2003-05-18 11:30:09 +0000 | [diff] [blame] | 225 | #endif |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 226 | |
| 227 | #ifndef CFG_POCMR2_MASK_ATTRIB |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 228 | #define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO) |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 229 | #else |
| 230 | #define POCMR2_MASK_ATTRIB CFG_POCMR2_MASK_ATTRIB |
| 231 | #endif |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 232 | |
| 233 | /* PCI bus configuration registers. |
| 234 | */ |
| 235 | |
| 236 | #define PCI_CLASS_BRIDGE_CTLR 0x06 |
| 237 | |
| 238 | |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 239 | static inline void pci_outl (u32 addr, u32 data) |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 240 | { |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 241 | *(volatile u32 *) addr = cpu_to_le32 (data); |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 242 | } |
| 243 | |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 244 | void pci_mpc8250_init (struct pci_controller *hose) |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 245 | { |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 246 | u16 tempShort; |
| 247 | |
| 248 | volatile immap_t *immap = (immap_t *) CFG_IMMR; |
| 249 | pci_dev_t host_devno = PCI_BDF (0, 0, 0); |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 250 | |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 251 | pci_setup_indirect (hose, CFG_IMMR + PCI_CFG_ADDR_REG, |
| 252 | CFG_IMMR + PCI_CFG_DATA_REG); |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 253 | |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 254 | /* |
| 255 | * Setting required to enable local bus for PCI (SIUMCR [LBPC]). |
| 256 | */ |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 257 | #ifdef CONFIG_MPC8266ADS |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 258 | immap->im_siu_conf.sc_siumcr = |
| 259 | (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) |
| 260 | | SIUMCR_LBPC01; |
Wolfgang Denk | 8cc89d9 | 2005-09-25 16:27:55 +0200 | [diff] [blame] | 261 | #elif defined CONFIG_MPC8272 |
Wolfgang Denk | 34ca9d3 | 2005-09-25 18:49:35 +0200 | [diff] [blame] | 262 | immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & |
| 263 | ~SIUMCR_BBD & |
| 264 | ~SIUMCR_ESE & |
| 265 | ~SIUMCR_PBSE & |
| 266 | ~SIUMCR_CDIS & |
| 267 | ~SIUMCR_DPPC11 & |
| 268 | ~SIUMCR_L2CPC11 & |
| 269 | ~SIUMCR_LBPC11 & |
| 270 | ~SIUMCR_APPC11 & |
| 271 | ~SIUMCR_CS10PC11 & |
| 272 | ~SIUMCR_BCTLC11 & |
| 273 | ~SIUMCR_MMR11) |
| 274 | | SIUMCR_DPPC11 |
| 275 | | SIUMCR_L2CPC01 |
| 276 | | SIUMCR_LBPC00 |
| 277 | | SIUMCR_APPC10 |
| 278 | | SIUMCR_CS10PC00 |
| 279 | | SIUMCR_BCTLC00 |
| 280 | | SIUMCR_MMR11; |
Heiko Schocher | 3ec4366 | 2006-12-21 17:17:02 +0100 | [diff] [blame] | 281 | #elif defined(CONFIG_TQM8272) |
Heiko Schocher | 609ed90 | 2007-03-21 08:45:17 +0100 | [diff] [blame] | 282 | /* nothing to do for this Board here */ |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 283 | #else |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 284 | /* |
| 285 | * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), |
| 286 | * and local bus for PCI (SIUMCR [LBPC]). |
| 287 | */ |
| 288 | immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & |
| 289 | ~SIUMCR_LBPC11 & |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 290 | ~SIUMCR_CS10PC11 & |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 291 | ~SIUMCR_LBPC11) | |
| 292 | SIUMCR_LBPC01 | |
| 293 | SIUMCR_CS10PC01 | |
| 294 | SIUMCR_APPC10; |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 295 | #endif |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 296 | |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 297 | /* Make PCI lowest priority */ |
| 298 | /* Each 4 bits is a device bus request and the MS 4bits |
| 299 | is highest priority */ |
| 300 | /* Bus 4bit value |
| 301 | --- ---------- |
| 302 | CPM high 0b0000 |
| 303 | CPM middle 0b0001 |
| 304 | CPM low 0b0010 |
| 305 | PCI reguest 0b0011 |
| 306 | Reserved 0b0100 |
| 307 | Reserved 0b0101 |
| 308 | Internal Core 0b0110 |
| 309 | External Master 1 0b0111 |
| 310 | External Master 2 0b1000 |
| 311 | External Master 3 0b1001 |
| 312 | The rest are reserved */ |
| 313 | immap->im_siu_conf.sc_ppc_alrh = 0x61207893; |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 314 | |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 315 | /* Park bus on core while modifying PCI Bus accesses */ |
| 316 | immap->im_siu_conf.sc_ppc_acr = 0x6; |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 317 | |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 318 | /* |
| 319 | * Set up master windows that allow the CPU to access PCI space. These |
| 320 | * windows are set up using the two SIU PCIBR registers. |
| 321 | */ |
| 322 | immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK; |
| 323 | immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE; |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 324 | |
Wolfgang Denk | 8cc89d9 | 2005-09-25 16:27:55 +0200 | [diff] [blame] | 325 | #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 |
wdenk | 792c44a | 2004-04-18 21:17:30 +0000 | [diff] [blame] | 326 | immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK; |
| 327 | immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL | PCIBR_ENABLE; |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 328 | #endif |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 329 | |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 330 | /* Release PCI RST (by default the PCI RST signal is held low) */ |
| 331 | immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN); |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 332 | |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 333 | /* give it some time */ |
| 334 | { |
Wolfgang Denk | 8cc89d9 | 2005-09-25 16:27:55 +0200 | [diff] [blame] | 335 | #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 336 | /* Give the PCI cards more time to initialize before query |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 337 | This might be good for other boards also |
| 338 | */ |
| 339 | int i; |
| 340 | |
| 341 | for (i = 0; i < 1000; ++i) |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 342 | #endif |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 343 | udelay (1000); |
| 344 | } |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 345 | |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 346 | /* |
| 347 | * Set up master window that allows the CPU to access PCI Memory (prefetch) |
| 348 | * space. This window is set up using the first set of Outbound ATU registers. |
| 349 | */ |
| 350 | immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12); /* PCI base */ |
| 351 | immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12); /* Local base */ |
| 352 | immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB); /* Size & attribute */ |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 353 | |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 354 | /* |
| 355 | * Set up master window that allows the CPU to access PCI Memory (non-prefetch) |
| 356 | * space. This window is set up using the second set of Outbound ATU registers. |
| 357 | */ |
| 358 | immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */ |
| 359 | immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */ |
| 360 | immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB); /* Size & attribute */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 361 | |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 362 | /* |
| 363 | * Set up master window that allows the CPU to access PCI IO space. This window |
| 364 | * is set up using the third set of Outbound ATU registers. |
| 365 | */ |
| 366 | immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */ |
| 367 | immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12); /* Local base */ |
| 368 | immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB); /* Size & attribute */ |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 369 | |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 370 | /* |
| 371 | * Set up slave window that allows PCI masters to access MPC826x local memory. |
| 372 | * This window is set up using the first set of Inbound ATU registers |
| 373 | */ |
| 374 | immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12); /* PCI base */ |
| 375 | immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */ |
| 376 | immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB); /* Size & attribute */ |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 377 | |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 378 | /* See above for description - puts PCI request as highest priority */ |
Wolfgang Denk | 8cc89d9 | 2005-09-25 16:27:55 +0200 | [diff] [blame] | 379 | #ifdef CONFIG_MPC8272 |
| 380 | immap->im_siu_conf.sc_ppc_alrh = 0x01236745; |
| 381 | #else |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 382 | immap->im_siu_conf.sc_ppc_alrh = 0x03124567; |
Wolfgang Denk | 8cc89d9 | 2005-09-25 16:27:55 +0200 | [diff] [blame] | 383 | #endif |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 384 | |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 385 | /* Park the bus on the PCI */ |
| 386 | immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI; |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 387 | |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 388 | /* Host mode - specify the bridge as a host-PCI bridge */ |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 389 | |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 390 | pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE, |
| 391 | PCI_CLASS_BRIDGE_CTLR); |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 392 | |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 393 | /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */ |
| 394 | pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort); |
| 395 | pci_hose_write_config_word (hose, host_devno, PCI_COMMAND, |
| 396 | tempShort | PCI_COMMAND_MASTER | |
| 397 | PCI_COMMAND_MEMORY); |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 398 | |
wdenk | abda5ca | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 399 | /* do some bridge init, should be done on all 8260 based bridges */ |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 400 | pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE, |
| 401 | 0x08); |
| 402 | pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER, |
| 403 | 0xF8); |
wdenk | abda5ca | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 404 | |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 405 | hose->first_busno = 0; |
| 406 | hose->last_busno = 0xff; |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 407 | |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 408 | /* System memory space */ |
Wolfgang Denk | e5357d0 | 2006-05-30 23:32:44 +0200 | [diff] [blame] | 409 | #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826 |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 410 | pci_set_region (hose->regions + 0, |
| 411 | PCI_SLV_MEM_BUS, |
| 412 | PCI_SLV_MEM_LOCAL, |
| 413 | gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 414 | #else |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 415 | pci_set_region (hose->regions + 0, |
| 416 | CFG_SDRAM_BASE, |
| 417 | CFG_SDRAM_BASE, |
| 418 | 0x4000000, PCI_REGION_MEM | PCI_REGION_MEMORY); |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 419 | #endif |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 420 | |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 421 | /* PCI memory space */ |
Wolfgang Denk | 34ca9d3 | 2005-09-25 18:49:35 +0200 | [diff] [blame] | 422 | #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 423 | pci_set_region (hose->regions + 1, |
| 424 | PCI_MSTR_MEMIO_BUS, |
| 425 | PCI_MSTR_MEMIO_LOCAL, |
| 426 | PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM); |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 427 | #else |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 428 | pci_set_region (hose->regions + 1, |
| 429 | PCI_MSTR_MEM_BUS, |
| 430 | PCI_MSTR_MEM_LOCAL, |
| 431 | PCI_MSTR_MEM_SIZE, PCI_REGION_MEM); |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 432 | #endif |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 433 | |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 434 | /* PCI I/O space */ |
| 435 | pci_set_region (hose->regions + 2, |
| 436 | PCI_MSTR_IO_BUS, |
| 437 | PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO); |
| 438 | |
| 439 | hose->region_count = 3; |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 440 | |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 441 | pci_register_hose (hose); |
| 442 | /* Mask off master abort machine checks */ |
| 443 | immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP); |
| 444 | eieio (); |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 445 | |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 446 | hose->last_busno = pci_hose_scan (hose); |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 447 | |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 448 | |
| 449 | /* clear the error in the error status register */ |
| 450 | immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP); |
| 451 | |
| 452 | /* unmask master abort machine checks */ |
| 453 | immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP); |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 454 | } |
| 455 | |
Matvejchikov Ilya | 8743c79 | 2008-07-06 13:57:00 +0400 | [diff] [blame] | 456 | #if defined(CONFIG_OF_LIBFDT) |
| 457 | void ft_pci_setup(void *blob, bd_t *bd) |
| 458 | { |
| 459 | do_fixup_by_prop_u32(blob, "device_type", "pci", 4, |
Wolfgang Denk | 20de6ac | 2008-08-12 12:10:11 +0200 | [diff] [blame] | 460 | "clock-frequency", gd->pci_clk, 1); |
Matvejchikov Ilya | 8743c79 | 2008-07-06 13:57:00 +0400 | [diff] [blame] | 461 | } |
| 462 | #endif |
| 463 | |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 464 | #endif /* CONFIG_PCI */ |