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git01.mediatek.com / filogic / uboot / c2308208df9d01048f223ca816d28401f95eb660 / . / include / configs / theadorable.h
blob: 45cd7e2b83ac371789ef3da451cccfdccf9155fd [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]2/*
3 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]4 */
5
6#ifndef _CONFIG_THEADORABLE_H
7#define _CONFIG_THEADORABLE_H
8
9/*
10 * High Level Configuration Options (easy to change)
11 */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]12
13/*
14 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
15 * for DDR ECC byte filling in the SPL before loading the main
16 * U-Boot into it.
17 */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]18#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
19
20/*
21 * Commands configuration
22 */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]23
24/*
25 * The debugging version enables USB support via defconfig.
26 * This version should also enable all other non-production
27 * interfaces / features.
28 */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]29
30/* I2C */
31#define CONFIG_SYS_I2C
32#define CONFIG_SYS_I2C_MVTWSI
33#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
Stefan Roese07b5e042016-04-08 15:58:29 +0200[diff] [blame]34#define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]35#define CONFIG_SYS_I2C_SLAVE 0x0
36#define CONFIG_SYS_I2C_SPEED 100000
37
38/* USB/EHCI configuration */
39#define CONFIG_EHCI_IS_TDI
40#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
41
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]42/* Environment in SPI NOR flash */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]43#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
44#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
45#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
46#define CONFIG_ENV_OVERWRITE
47
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]48#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
49
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]50/* Keep device tree and initrd in lower memory so the kernel can access them */
51#define CONFIG_EXTRA_ENV_SETTINGS \
52 "fdt_high=0x10000000\0" \
53 "initrd_high=0x10000000\0"
54
55/* SATA support */
56#define CONFIG_SYS_SATA_MAX_DEVICE 1
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]57#define CONFIG_LBA48
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]58
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]59/* Enable LCD and reserve 512KB from top of memory*/
60#define CONFIG_SYS_MEM_TOP_HIDE 0x80000
61
Stefan Roesed64c1132019-01-30 08:54:13 +0100[diff] [blame]62#define CONFIG_BMP_16BPP
63#define CONFIG_BMP_24BPP
64#define CONFIG_BMP_32BPP
65
Stefan Roesef0547582016-02-12 14:24:07 +0100[diff] [blame]66/* FPGA programming support */
Stefan Roesef0547582016-02-12 14:24:07 +0100[diff] [blame]67#define CONFIG_FPGA_STRATIX_V
68
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]69/*
Stefan Roese1a4e9802016-04-07 10:48:14 +0200[diff] [blame]70 * Bootcounter
71 */
Stefan Roese1a4e9802016-04-07 10:48:14 +0200[diff] [blame]72/* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
73#define BOOTCOUNT_ADDR 0x1000
74
75/*
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]76 * mv-common.h should be defined after CMD configs since it used them
77 * to enable certain macros
78 */
79#include "mv-common.h"
80
81/*
82 * Memory layout while starting into the bin_hdr via the
83 * BootROM:
84 *
85 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
86 * 0x4000.4030 bin_hdr start address
87 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
88 * 0x4007.fffc BootROM stack top
89 *
90 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
91 * L2 cache thus cannot be used.
92 */
93
94/* SPL */
95/* Defines for SPL */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]96#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
97
98#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
99#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
100
101#ifdef CONFIG_SPL_BUILD
102#define CONFIG_SYS_MALLOC_SIMPLE
103#endif
104
105#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
106#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
107
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]108/* SPL related SPI defines */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]109#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
110
111/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
112#define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */
113
114#endif /* _CONFIG_THEADORABLE_H */