blob: f555357af21362f3541bb860ad67bc517b6e0a53 [file] [log] [blame]
developerdc5a9aa2018-11-15 10:08:04 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * MediaTek SD/MMC Card Interface driver
4 *
5 * Copyright (C) 2018 MediaTek Inc.
6 * Author: Weijie Gao <weijie.gao@mediatek.com>
7 */
8
9#include <clk.h>
10#include <common.h>
11#include <dm.h>
12#include <mmc.h>
13#include <errno.h>
14#include <malloc.h>
15#include <stdbool.h>
developer7462c842019-07-19 11:04:47 +080016#include <watchdog.h>
developerdc5a9aa2018-11-15 10:08:04 +080017#include <asm/gpio.h>
18#include <dm/pinctrl.h>
19#include <linux/bitops.h>
20#include <linux/io.h>
21#include <linux/iopoll.h>
22
23/* MSDC_CFG */
24#define MSDC_CFG_HS400_CK_MODE_EXT BIT(22)
25#define MSDC_CFG_CKMOD_EXT_M 0x300000
26#define MSDC_CFG_CKMOD_EXT_S 20
27#define MSDC_CFG_CKDIV_EXT_M 0xfff00
28#define MSDC_CFG_CKDIV_EXT_S 8
29#define MSDC_CFG_HS400_CK_MODE BIT(18)
30#define MSDC_CFG_CKMOD_M 0x30000
31#define MSDC_CFG_CKMOD_S 16
32#define MSDC_CFG_CKDIV_M 0xff00
33#define MSDC_CFG_CKDIV_S 8
34#define MSDC_CFG_CKSTB BIT(7)
35#define MSDC_CFG_PIO BIT(3)
36#define MSDC_CFG_RST BIT(2)
37#define MSDC_CFG_CKPDN BIT(1)
38#define MSDC_CFG_MODE BIT(0)
39
40/* MSDC_IOCON */
41#define MSDC_IOCON_W_DSPL BIT(8)
42#define MSDC_IOCON_DSPL BIT(2)
43#define MSDC_IOCON_RSPL BIT(1)
44
45/* MSDC_PS */
46#define MSDC_PS_DAT0 BIT(16)
47#define MSDC_PS_CDDBCE_M 0xf000
48#define MSDC_PS_CDDBCE_S 12
49#define MSDC_PS_CDSTS BIT(1)
50#define MSDC_PS_CDEN BIT(0)
51
52/* #define MSDC_INT(EN) */
53#define MSDC_INT_ACMDRDY BIT(3)
54#define MSDC_INT_ACMDTMO BIT(4)
55#define MSDC_INT_ACMDCRCERR BIT(5)
56#define MSDC_INT_CMDRDY BIT(8)
57#define MSDC_INT_CMDTMO BIT(9)
58#define MSDC_INT_RSPCRCERR BIT(10)
59#define MSDC_INT_XFER_COMPL BIT(12)
60#define MSDC_INT_DATTMO BIT(14)
61#define MSDC_INT_DATCRCERR BIT(15)
62
63/* MSDC_FIFOCS */
64#define MSDC_FIFOCS_CLR BIT(31)
65#define MSDC_FIFOCS_TXCNT_M 0xff0000
66#define MSDC_FIFOCS_TXCNT_S 16
67#define MSDC_FIFOCS_RXCNT_M 0xff
68#define MSDC_FIFOCS_RXCNT_S 0
69
70/* #define SDC_CFG */
71#define SDC_CFG_DTOC_M 0xff000000
72#define SDC_CFG_DTOC_S 24
73#define SDC_CFG_SDIOIDE BIT(20)
74#define SDC_CFG_SDIO BIT(19)
75#define SDC_CFG_BUSWIDTH_M 0x30000
76#define SDC_CFG_BUSWIDTH_S 16
77
78/* SDC_CMD */
79#define SDC_CMD_BLK_LEN_M 0xfff0000
80#define SDC_CMD_BLK_LEN_S 16
81#define SDC_CMD_STOP BIT(14)
82#define SDC_CMD_WR BIT(13)
83#define SDC_CMD_DTYPE_M 0x1800
84#define SDC_CMD_DTYPE_S 11
85#define SDC_CMD_RSPTYP_M 0x380
86#define SDC_CMD_RSPTYP_S 7
87#define SDC_CMD_CMD_M 0x3f
88#define SDC_CMD_CMD_S 0
89
90/* SDC_STS */
91#define SDC_STS_CMDBUSY BIT(1)
92#define SDC_STS_SDCBUSY BIT(0)
93
94/* SDC_ADV_CFG0 */
95#define SDC_RX_ENHANCE_EN BIT(20)
96
97/* PATCH_BIT0 */
98#define MSDC_INT_DAT_LATCH_CK_SEL_M 0x380
99#define MSDC_INT_DAT_LATCH_CK_SEL_S 7
100
101/* PATCH_BIT1 */
102#define MSDC_PB1_STOP_DLY_M 0xf00
103#define MSDC_PB1_STOP_DLY_S 8
104
105/* PATCH_BIT2 */
106#define MSDC_PB2_CRCSTSENSEL_M 0xe0000000
107#define MSDC_PB2_CRCSTSENSEL_S 29
108#define MSDC_PB2_CFGCRCSTS BIT(28)
109#define MSDC_PB2_RESPSTSENSEL_M 0x70000
110#define MSDC_PB2_RESPSTSENSEL_S 16
111#define MSDC_PB2_CFGRESP BIT(15)
112#define MSDC_PB2_RESPWAIT_M 0x0c
113#define MSDC_PB2_RESPWAIT_S 2
114
115/* PAD_TUNE */
116#define MSDC_PAD_TUNE_CMDRRDLY_M 0x7c00000
117#define MSDC_PAD_TUNE_CMDRRDLY_S 22
118#define MSDC_PAD_TUNE_CMD_SEL BIT(21)
119#define MSDC_PAD_TUNE_CMDRDLY_M 0x1f0000
120#define MSDC_PAD_TUNE_CMDRDLY_S 16
121#define MSDC_PAD_TUNE_RXDLYSEL BIT(15)
122#define MSDC_PAD_TUNE_RD_SEL BIT(13)
123#define MSDC_PAD_TUNE_DATRRDLY_M 0x1f00
124#define MSDC_PAD_TUNE_DATRRDLY_S 8
125#define MSDC_PAD_TUNE_DATWRDLY_M 0x1f
126#define MSDC_PAD_TUNE_DATWRDLY_S 0
127
128/* EMMC50_CFG0 */
129#define EMMC50_CFG_CFCSTS_SEL BIT(4)
130
131/* SDC_FIFO_CFG */
132#define SDC_FIFO_CFG_WRVALIDSEL BIT(24)
133#define SDC_FIFO_CFG_RDVALIDSEL BIT(25)
134
135/* SDC_CFG_BUSWIDTH */
136#define MSDC_BUS_1BITS 0x0
137#define MSDC_BUS_4BITS 0x1
138#define MSDC_BUS_8BITS 0x2
139
140#define MSDC_FIFO_SIZE 128
141
142#define PAD_DELAY_MAX 32
143
144#define DEFAULT_CD_DEBOUNCE 8
145
146#define CMD_INTS_MASK \
147 (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO)
148
149#define DATA_INTS_MASK \
150 (MSDC_INT_XFER_COMPL | MSDC_INT_DATTMO | MSDC_INT_DATCRCERR)
151
152/* Register offset */
153struct mtk_sd_regs {
154 u32 msdc_cfg;
155 u32 msdc_iocon;
156 u32 msdc_ps;
157 u32 msdc_int;
158 u32 msdc_inten;
159 u32 msdc_fifocs;
160 u32 msdc_txdata;
161 u32 msdc_rxdata;
162 u32 reserved0[4];
163 u32 sdc_cfg;
164 u32 sdc_cmd;
165 u32 sdc_arg;
166 u32 sdc_sts;
167 u32 sdc_resp[4];
168 u32 sdc_blk_num;
169 u32 sdc_vol_chg;
170 u32 sdc_csts;
171 u32 sdc_csts_en;
172 u32 sdc_datcrc_sts;
173 u32 sdc_adv_cfg0;
174 u32 reserved1[2];
175 u32 emmc_cfg0;
176 u32 emmc_cfg1;
177 u32 emmc_sts;
178 u32 emmc_iocon;
179 u32 sd_acmd_resp;
180 u32 sd_acmd19_trg;
181 u32 sd_acmd19_sts;
182 u32 dma_sa_high4bit;
183 u32 dma_sa;
184 u32 dma_ca;
185 u32 dma_ctrl;
186 u32 dma_cfg;
187 u32 sw_dbg_sel;
188 u32 sw_dbg_out;
189 u32 dma_length;
190 u32 reserved2;
191 u32 patch_bit0;
192 u32 patch_bit1;
193 u32 patch_bit2;
194 u32 reserved3;
195 u32 dat0_tune_crc;
196 u32 dat1_tune_crc;
197 u32 dat2_tune_crc;
198 u32 dat3_tune_crc;
199 u32 cmd_tune_crc;
200 u32 sdio_tune_wind;
201 u32 reserved4[5];
202 u32 pad_tune;
203 u32 pad_tune0;
204 u32 pad_tune1;
205 u32 dat_rd_dly[4];
206 u32 reserved5[2];
207 u32 hw_dbg_sel;
208 u32 main_ver;
209 u32 eco_ver;
210 u32 reserved6[27];
211 u32 pad_ds_tune;
212 u32 reserved7[31];
213 u32 emmc50_cfg0;
214 u32 reserved8[7];
215 u32 sdc_fifo_cfg;
216};
217
218struct msdc_compatible {
219 u8 clk_div_bits;
220 bool pad_tune0;
221 bool async_fifo;
222 bool data_tune;
223 bool busy_check;
224 bool stop_clk_fix;
225 bool enhance_rx;
226};
227
228struct msdc_delay_phase {
229 u8 maxlen;
230 u8 start;
231 u8 final_phase;
232};
233
234struct msdc_plat {
235 struct mmc_config cfg;
236 struct mmc mmc;
237};
238
239struct msdc_tune_para {
240 u32 iocon;
241 u32 pad_tune;
242};
243
244struct msdc_host {
245 struct mtk_sd_regs *base;
246 struct mmc *mmc;
247
248 struct msdc_compatible *dev_comp;
249
250 struct clk src_clk; /* for SD/MMC bus clock */
Fabien Parent297fa1a2019-03-24 16:46:32 +0100251 struct clk src_clk_cg; /* optional, MSDC source clock control gate */
developerdc5a9aa2018-11-15 10:08:04 +0800252 struct clk h_clk; /* MSDC core clock */
253
254 u32 src_clk_freq; /* source clock */
255 u32 mclk; /* mmc framework required bus clock */
256 u32 sclk; /* actual calculated bus clock */
257
258 /* operation timeout clocks */
259 u32 timeout_ns;
260 u32 timeout_clks;
261
262 /* tuning options */
263 u32 hs400_ds_delay;
264 u32 hs200_cmd_int_delay;
265 u32 hs200_write_int_delay;
266 u32 latch_ck;
267 u32 r_smpl; /* sample edge */
268 bool hs400_mode;
269
270 /* whether to use gpio detection or built-in hw detection */
271 bool builtin_cd;
272
273 /* card detection / write protection GPIOs */
Fabien Parent8ed608a2019-03-24 16:46:34 +0100274#if CONFIG_IS_ENABLED(DM_GPIO)
developerdc5a9aa2018-11-15 10:08:04 +0800275 struct gpio_desc gpio_wp;
276 struct gpio_desc gpio_cd;
277#endif
278
279 uint last_resp_type;
280 uint last_data_write;
281
282 enum bus_mode timing;
283
284 struct msdc_tune_para def_tune_para;
285 struct msdc_tune_para saved_tune_para;
286};
287
288static void msdc_reset_hw(struct msdc_host *host)
289{
290 u32 reg;
291
292 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_RST);
293
294 readl_poll_timeout(&host->base->msdc_cfg, reg,
295 !(reg & MSDC_CFG_RST), 1000000);
296}
297
298static void msdc_fifo_clr(struct msdc_host *host)
299{
300 u32 reg;
301
302 setbits_le32(&host->base->msdc_fifocs, MSDC_FIFOCS_CLR);
303
304 readl_poll_timeout(&host->base->msdc_fifocs, reg,
305 !(reg & MSDC_FIFOCS_CLR), 1000000);
306}
307
308static u32 msdc_fifo_rx_bytes(struct msdc_host *host)
309{
310 return (readl(&host->base->msdc_fifocs) &
311 MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S;
312}
313
314static u32 msdc_fifo_tx_bytes(struct msdc_host *host)
315{
316 return (readl(&host->base->msdc_fifocs) &
317 MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S;
318}
319
320static u32 msdc_cmd_find_resp(struct msdc_host *host, struct mmc_cmd *cmd)
321{
322 u32 resp;
323
324 switch (cmd->resp_type) {
325 /* Actually, R1, R5, R6, R7 are the same */
326 case MMC_RSP_R1:
327 resp = 0x1;
328 break;
329 case MMC_RSP_R1b:
330 resp = 0x7;
331 break;
332 case MMC_RSP_R2:
333 resp = 0x2;
334 break;
335 case MMC_RSP_R3:
336 resp = 0x3;
337 break;
338 case MMC_RSP_NONE:
339 default:
340 resp = 0x0;
341 break;
342 }
343
344 return resp;
345}
346
347static u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
348 struct mmc_cmd *cmd,
349 struct mmc_data *data)
350{
351 u32 opcode = cmd->cmdidx;
352 u32 resp_type = msdc_cmd_find_resp(host, cmd);
353 uint blocksize = 0;
354 u32 dtype = 0;
355 u32 rawcmd = 0;
356
357 switch (opcode) {
358 case MMC_CMD_WRITE_MULTIPLE_BLOCK:
359 case MMC_CMD_READ_MULTIPLE_BLOCK:
360 dtype = 2;
361 break;
362 case MMC_CMD_WRITE_SINGLE_BLOCK:
363 case MMC_CMD_READ_SINGLE_BLOCK:
364 case SD_CMD_APP_SEND_SCR:
365 dtype = 1;
366 break;
367 case SD_CMD_SWITCH_FUNC: /* same as MMC_CMD_SWITCH */
368 case SD_CMD_SEND_IF_COND: /* same as MMC_CMD_SEND_EXT_CSD */
369 case SD_CMD_APP_SD_STATUS: /* same as MMC_CMD_SEND_STATUS */
370 if (data)
371 dtype = 1;
372 }
373
374 if (data) {
375 if (data->flags == MMC_DATA_WRITE)
376 rawcmd |= SDC_CMD_WR;
377
378 if (data->blocks > 1)
379 dtype = 2;
380
381 blocksize = data->blocksize;
382 }
383
384 rawcmd |= ((opcode << SDC_CMD_CMD_S) & SDC_CMD_CMD_M) |
385 ((resp_type << SDC_CMD_RSPTYP_S) & SDC_CMD_RSPTYP_M) |
386 ((blocksize << SDC_CMD_BLK_LEN_S) & SDC_CMD_BLK_LEN_M) |
387 ((dtype << SDC_CMD_DTYPE_S) & SDC_CMD_DTYPE_M);
388
389 if (opcode == MMC_CMD_STOP_TRANSMISSION)
390 rawcmd |= SDC_CMD_STOP;
391
392 return rawcmd;
393}
394
395static int msdc_cmd_done(struct msdc_host *host, int events,
396 struct mmc_cmd *cmd)
397{
398 u32 *rsp = cmd->response;
399 int ret = 0;
400
401 if (cmd->resp_type & MMC_RSP_PRESENT) {
402 if (cmd->resp_type & MMC_RSP_136) {
403 rsp[0] = readl(&host->base->sdc_resp[3]);
404 rsp[1] = readl(&host->base->sdc_resp[2]);
405 rsp[2] = readl(&host->base->sdc_resp[1]);
406 rsp[3] = readl(&host->base->sdc_resp[0]);
407 } else {
408 rsp[0] = readl(&host->base->sdc_resp[0]);
409 }
410 }
411
412 if (!(events & MSDC_INT_CMDRDY)) {
413 if (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK &&
414 cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200)
415 /*
416 * should not clear fifo/interrupt as the tune data
417 * may have alreay come.
418 */
419 msdc_reset_hw(host);
420
421 if (events & MSDC_INT_CMDTMO)
422 ret = -ETIMEDOUT;
423 else
424 ret = -EIO;
425 }
426
427 return ret;
428}
429
430static bool msdc_cmd_is_ready(struct msdc_host *host)
431{
432 int ret;
433 u32 reg;
434
435 /* The max busy time we can endure is 20ms */
436 ret = readl_poll_timeout(&host->base->sdc_sts, reg,
437 !(reg & SDC_STS_CMDBUSY), 20000);
438
439 if (ret) {
440 pr_err("CMD bus busy detected\n");
441 msdc_reset_hw(host);
442 return false;
443 }
444
445 if (host->last_resp_type == MMC_RSP_R1b && host->last_data_write) {
446 ret = readl_poll_timeout(&host->base->msdc_ps, reg,
447 reg & MSDC_PS_DAT0, 1000000);
448
449 if (ret) {
450 pr_err("Card stuck in programming state!\n");
451 msdc_reset_hw(host);
452 return false;
453 }
454 }
455
456 return true;
457}
458
459static int msdc_start_command(struct msdc_host *host, struct mmc_cmd *cmd,
460 struct mmc_data *data)
461{
462 u32 rawcmd;
463 u32 status;
464 u32 blocks = 0;
465 int ret;
466
467 if (!msdc_cmd_is_ready(host))
468 return -EIO;
469
470 msdc_fifo_clr(host);
471
472 host->last_resp_type = cmd->resp_type;
473 host->last_data_write = 0;
474
475 rawcmd = msdc_cmd_prepare_raw_cmd(host, cmd, data);
476
477 if (data)
478 blocks = data->blocks;
479
480 writel(CMD_INTS_MASK, &host->base->msdc_int);
481 writel(blocks, &host->base->sdc_blk_num);
482 writel(cmd->cmdarg, &host->base->sdc_arg);
483 writel(rawcmd, &host->base->sdc_cmd);
484
485 ret = readl_poll_timeout(&host->base->msdc_int, status,
486 status & CMD_INTS_MASK, 1000000);
487
488 if (ret)
489 status = MSDC_INT_CMDTMO;
490
491 return msdc_cmd_done(host, status, cmd);
492}
493
494static void msdc_fifo_read(struct msdc_host *host, u8 *buf, u32 size)
495{
496 u32 *wbuf;
497
498 while ((size_t)buf % 4) {
499 *buf++ = readb(&host->base->msdc_rxdata);
500 size--;
501 }
502
503 wbuf = (u32 *)buf;
504 while (size >= 4) {
505 *wbuf++ = readl(&host->base->msdc_rxdata);
506 size -= 4;
507 }
508
509 buf = (u8 *)wbuf;
510 while (size) {
511 *buf++ = readb(&host->base->msdc_rxdata);
512 size--;
513 }
514}
515
516static void msdc_fifo_write(struct msdc_host *host, const u8 *buf, u32 size)
517{
518 const u32 *wbuf;
519
520 while ((size_t)buf % 4) {
521 writeb(*buf++, &host->base->msdc_txdata);
522 size--;
523 }
524
525 wbuf = (const u32 *)buf;
526 while (size >= 4) {
527 writel(*wbuf++, &host->base->msdc_txdata);
528 size -= 4;
529 }
530
531 buf = (const u8 *)wbuf;
532 while (size) {
533 writeb(*buf++, &host->base->msdc_txdata);
534 size--;
535 }
536}
537
538static int msdc_pio_read(struct msdc_host *host, u8 *ptr, u32 size)
539{
540 u32 status;
541 u32 chksz;
542 int ret = 0;
543
544 while (1) {
545 status = readl(&host->base->msdc_int);
546 writel(status, &host->base->msdc_int);
547 status &= DATA_INTS_MASK;
548
549 if (status & MSDC_INT_DATCRCERR) {
550 ret = -EIO;
551 break;
552 }
553
554 if (status & MSDC_INT_DATTMO) {
555 ret = -ETIMEDOUT;
556 break;
557 }
558
Fabien Parent79a60732019-01-17 18:06:00 +0100559 chksz = min(size, (u32)MSDC_FIFO_SIZE);
560
561 if (msdc_fifo_rx_bytes(host) >= chksz) {
562 msdc_fifo_read(host, ptr, chksz);
563 ptr += chksz;
564 size -= chksz;
565 }
566
developerdc5a9aa2018-11-15 10:08:04 +0800567 if (status & MSDC_INT_XFER_COMPL) {
568 if (size) {
569 pr_err("data not fully read\n");
570 ret = -EIO;
571 }
572
573 break;
574 }
Fabien Parent79a60732019-01-17 18:06:00 +0100575}
developerdc5a9aa2018-11-15 10:08:04 +0800576
577 return ret;
578}
579
580static int msdc_pio_write(struct msdc_host *host, const u8 *ptr, u32 size)
581{
582 u32 status;
583 u32 chksz;
584 int ret = 0;
585
586 while (1) {
587 status = readl(&host->base->msdc_int);
588 writel(status, &host->base->msdc_int);
589 status &= DATA_INTS_MASK;
590
591 if (status & MSDC_INT_DATCRCERR) {
592 ret = -EIO;
593 break;
594 }
595
596 if (status & MSDC_INT_DATTMO) {
597 ret = -ETIMEDOUT;
598 break;
599 }
600
601 if (status & MSDC_INT_XFER_COMPL) {
602 if (size) {
603 pr_err("data not fully written\n");
604 ret = -EIO;
605 }
606
607 break;
608 }
609
610 chksz = min(size, (u32)MSDC_FIFO_SIZE);
611
612 if (MSDC_FIFO_SIZE - msdc_fifo_tx_bytes(host) >= chksz) {
613 msdc_fifo_write(host, ptr, chksz);
614 ptr += chksz;
615 size -= chksz;
616 }
617 }
618
619 return ret;
620}
621
622static int msdc_start_data(struct msdc_host *host, struct mmc_data *data)
623{
624 u32 size;
625 int ret;
626
developer7462c842019-07-19 11:04:47 +0800627 WATCHDOG_RESET();
628
developerdc5a9aa2018-11-15 10:08:04 +0800629 if (data->flags == MMC_DATA_WRITE)
630 host->last_data_write = 1;
631
632 writel(DATA_INTS_MASK, &host->base->msdc_int);
633
634 size = data->blocks * data->blocksize;
635
636 if (data->flags == MMC_DATA_WRITE)
637 ret = msdc_pio_write(host, (const u8 *)data->src, size);
638 else
639 ret = msdc_pio_read(host, (u8 *)data->dest, size);
640
641 if (ret) {
642 msdc_reset_hw(host);
643 msdc_fifo_clr(host);
644 }
645
646 return ret;
647}
648
649static int msdc_ops_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
650 struct mmc_data *data)
651{
652 struct msdc_host *host = dev_get_priv(dev);
653 int ret;
654
655 ret = msdc_start_command(host, cmd, data);
656 if (ret)
657 return ret;
658
659 if (data)
660 return msdc_start_data(host, data);
661
662 return 0;
663}
664
665static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
666{
667 u32 timeout, clk_ns;
668 u32 mode = 0;
669
670 host->timeout_ns = ns;
671 host->timeout_clks = clks;
672
673 if (host->sclk == 0) {
674 timeout = 0;
675 } else {
676 clk_ns = 1000000000UL / host->sclk;
677 timeout = (ns + clk_ns - 1) / clk_ns + clks;
678 /* unit is 1048576 sclk cycles */
679 timeout = (timeout + (0x1 << 20) - 1) >> 20;
680 if (host->dev_comp->clk_div_bits == 8)
681 mode = (readl(&host->base->msdc_cfg) &
682 MSDC_CFG_CKMOD_M) >> MSDC_CFG_CKMOD_S;
683 else
684 mode = (readl(&host->base->msdc_cfg) &
685 MSDC_CFG_CKMOD_EXT_M) >> MSDC_CFG_CKMOD_EXT_S;
686 /* DDR mode will double the clk cycles for data timeout */
687 timeout = mode >= 2 ? timeout * 2 : timeout;
688 timeout = timeout > 1 ? timeout - 1 : 0;
689 timeout = timeout > 255 ? 255 : timeout;
690 }
691
692 clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
693 timeout << SDC_CFG_DTOC_S);
694}
695
696static void msdc_set_buswidth(struct msdc_host *host, u32 width)
697{
698 u32 val = readl(&host->base->sdc_cfg);
699
700 val &= ~SDC_CFG_BUSWIDTH_M;
701
702 switch (width) {
703 default:
704 case 1:
705 val |= (MSDC_BUS_1BITS << SDC_CFG_BUSWIDTH_S);
706 break;
707 case 4:
708 val |= (MSDC_BUS_4BITS << SDC_CFG_BUSWIDTH_S);
709 break;
710 case 8:
711 val |= (MSDC_BUS_8BITS << SDC_CFG_BUSWIDTH_S);
712 break;
713 }
714
715 writel(val, &host->base->sdc_cfg);
716}
717
718static void msdc_set_mclk(struct msdc_host *host, enum bus_mode timing, u32 hz)
719{
720 u32 mode;
721 u32 div;
722 u32 sclk;
723 u32 reg;
724
725 if (!hz) {
726 host->mclk = 0;
727 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
728 return;
729 }
730
731 if (host->dev_comp->clk_div_bits == 8)
732 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_HS400_CK_MODE);
733 else
734 clrbits_le32(&host->base->msdc_cfg,
735 MSDC_CFG_HS400_CK_MODE_EXT);
736
737 if (timing == UHS_DDR50 || timing == MMC_DDR_52 ||
738 timing == MMC_HS_400) {
739 if (timing == MMC_HS_400)
740 mode = 0x3;
741 else
742 mode = 0x2; /* ddr mode and use divisor */
743
744 if (hz >= (host->src_clk_freq >> 2)) {
745 div = 0; /* mean div = 1/4 */
746 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
747 } else {
748 div = (host->src_clk_freq + ((hz << 2) - 1)) /
749 (hz << 2);
750 sclk = (host->src_clk_freq >> 2) / div;
751 div = (div >> 1);
752 }
753
754 if (timing == MMC_HS_400 && hz >= (host->src_clk_freq >> 1)) {
755 if (host->dev_comp->clk_div_bits == 8)
756 setbits_le32(&host->base->msdc_cfg,
757 MSDC_CFG_HS400_CK_MODE);
758 else
759 setbits_le32(&host->base->msdc_cfg,
760 MSDC_CFG_HS400_CK_MODE_EXT);
761
762 sclk = host->src_clk_freq >> 1;
763 div = 0; /* div is ignore when bit18 is set */
764 }
765 } else if (hz >= host->src_clk_freq) {
766 mode = 0x1; /* no divisor */
767 div = 0;
768 sclk = host->src_clk_freq;
769 } else {
770 mode = 0x0; /* use divisor */
771 if (hz >= (host->src_clk_freq >> 1)) {
772 div = 0; /* mean div = 1/2 */
773 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
774 } else {
775 div = (host->src_clk_freq + ((hz << 2) - 1)) /
776 (hz << 2);
777 sclk = (host->src_clk_freq >> 2) / div;
778 }
779 }
780
781 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
782
783 if (host->dev_comp->clk_div_bits == 8) {
784 div = min(div, (u32)(MSDC_CFG_CKDIV_M >> MSDC_CFG_CKDIV_S));
785 clrsetbits_le32(&host->base->msdc_cfg,
786 MSDC_CFG_CKMOD_M | MSDC_CFG_CKDIV_M,
787 (mode << MSDC_CFG_CKMOD_S) |
788 (div << MSDC_CFG_CKDIV_S));
789 } else {
790 div = min(div, (u32)(MSDC_CFG_CKDIV_EXT_M >>
791 MSDC_CFG_CKDIV_EXT_S));
792 clrsetbits_le32(&host->base->msdc_cfg,
793 MSDC_CFG_CKMOD_EXT_M | MSDC_CFG_CKDIV_EXT_M,
794 (mode << MSDC_CFG_CKMOD_EXT_S) |
795 (div << MSDC_CFG_CKDIV_EXT_S));
796 }
797
798 readl_poll_timeout(&host->base->msdc_cfg, reg,
799 reg & MSDC_CFG_CKSTB, 1000000);
800
801 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
802 host->sclk = sclk;
803 host->mclk = hz;
804 host->timing = timing;
805
806 /* needed because clk changed. */
807 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
808
809 /*
810 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
811 * tune result of hs200/200Mhz is not suitable for 50Mhz
812 */
813 if (host->sclk <= 52000000) {
814 writel(host->def_tune_para.iocon, &host->base->msdc_iocon);
815 writel(host->def_tune_para.pad_tune,
816 &host->base->pad_tune);
817 } else {
818 writel(host->saved_tune_para.iocon, &host->base->msdc_iocon);
819 writel(host->saved_tune_para.pad_tune,
820 &host->base->pad_tune);
821 }
822
823 dev_dbg(dev, "sclk: %d, timing: %d\n", host->sclk, timing);
824}
825
826static int msdc_ops_set_ios(struct udevice *dev)
827{
828 struct msdc_plat *plat = dev_get_platdata(dev);
829 struct msdc_host *host = dev_get_priv(dev);
830 struct mmc *mmc = &plat->mmc;
831 uint clock = mmc->clock;
832
833 msdc_set_buswidth(host, mmc->bus_width);
834
835 if (mmc->clk_disable)
836 clock = 0;
837 else if (clock < mmc->cfg->f_min)
838 clock = mmc->cfg->f_min;
839
840 if (host->mclk != clock || host->timing != mmc->selected_mode)
841 msdc_set_mclk(host, mmc->selected_mode, clock);
842
843 return 0;
844}
845
846static int msdc_ops_get_cd(struct udevice *dev)
847{
848 struct msdc_host *host = dev_get_priv(dev);
849 u32 val;
850
851 if (host->builtin_cd) {
852 val = readl(&host->base->msdc_ps);
853 return !(val & MSDC_PS_CDSTS);
854 }
855
Fabien Parent8ed608a2019-03-24 16:46:34 +0100856#if CONFIG_IS_ENABLED(DM_GPIO)
developerdc5a9aa2018-11-15 10:08:04 +0800857 if (!host->gpio_cd.dev)
858 return 1;
859
860 return dm_gpio_get_value(&host->gpio_cd);
861#else
862 return 1;
863#endif
864}
865
866static int msdc_ops_get_wp(struct udevice *dev)
867{
Fabien Parent8ed608a2019-03-24 16:46:34 +0100868#if CONFIG_IS_ENABLED(DM_GPIO)
developerdc5a9aa2018-11-15 10:08:04 +0800869 struct msdc_host *host = dev_get_priv(dev);
870
developerdc5a9aa2018-11-15 10:08:04 +0800871 if (!host->gpio_wp.dev)
872 return 0;
873
874 return !dm_gpio_get_value(&host->gpio_wp);
875#else
876 return 0;
877#endif
878}
879
880#ifdef MMC_SUPPORTS_TUNING
881static u32 test_delay_bit(u32 delay, u32 bit)
882{
883 bit %= PAD_DELAY_MAX;
884 return delay & (1 << bit);
885}
886
887static int get_delay_len(u32 delay, u32 start_bit)
888{
889 int i;
890
891 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
892 if (test_delay_bit(delay, start_bit + i) == 0)
893 return i;
894 }
895
896 return PAD_DELAY_MAX - start_bit;
897}
898
899static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
900{
901 int start = 0, len = 0;
902 int start_final = 0, len_final = 0;
903 u8 final_phase = 0xff;
904 struct msdc_delay_phase delay_phase = { 0, };
905
906 if (delay == 0) {
907 dev_err(dev, "phase error: [map:%x]\n", delay);
908 delay_phase.final_phase = final_phase;
909 return delay_phase;
910 }
911
912 while (start < PAD_DELAY_MAX) {
913 len = get_delay_len(delay, start);
914 if (len_final < len) {
915 start_final = start;
916 len_final = len;
917 }
918
919 start += len ? len : 1;
920 if (len >= 12 && start_final < 4)
921 break;
922 }
923
924 /* The rule is to find the smallest delay cell */
925 if (start_final == 0)
926 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
927 else
928 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
929
930 dev_info(dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
931 delay, len_final, final_phase);
932
933 delay_phase.maxlen = len_final;
934 delay_phase.start = start_final;
935 delay_phase.final_phase = final_phase;
936 return delay_phase;
937}
938
939static int msdc_tune_response(struct udevice *dev, u32 opcode)
940{
941 struct msdc_plat *plat = dev_get_platdata(dev);
942 struct msdc_host *host = dev_get_priv(dev);
943 struct mmc *mmc = &plat->mmc;
944 u32 rise_delay = 0, fall_delay = 0;
945 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
946 struct msdc_delay_phase internal_delay_phase;
947 u8 final_delay, final_maxlen;
948 u32 internal_delay = 0;
949 void __iomem *tune_reg = &host->base->pad_tune;
950 int cmd_err;
951 int i, j;
952
953 if (host->dev_comp->pad_tune0)
954 tune_reg = &host->base->pad_tune0;
955
956 if (mmc->selected_mode == MMC_HS_200 ||
957 mmc->selected_mode == UHS_SDR104)
958 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
959 host->hs200_cmd_int_delay <<
960 MSDC_PAD_TUNE_CMDRRDLY_S);
961
962 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
963
964 for (i = 0; i < PAD_DELAY_MAX; i++) {
965 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
966 i << MSDC_PAD_TUNE_CMDRDLY_S);
967
968 for (j = 0; j < 3; j++) {
969 mmc_send_tuning(mmc, opcode, &cmd_err);
970 if (!cmd_err) {
971 rise_delay |= (1 << i);
972 } else {
973 rise_delay &= ~(1 << i);
974 break;
975 }
976 }
977 }
978
979 final_rise_delay = get_best_delay(host, rise_delay);
980 /* if rising edge has enough margin, do not scan falling edge */
981 if (final_rise_delay.maxlen >= 12 ||
982 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
983 goto skip_fall;
984
985 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
986 for (i = 0; i < PAD_DELAY_MAX; i++) {
987 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
988 i << MSDC_PAD_TUNE_CMDRDLY_S);
989
990 for (j = 0; j < 3; j++) {
991 mmc_send_tuning(mmc, opcode, &cmd_err);
992 if (!cmd_err) {
993 fall_delay |= (1 << i);
994 } else {
995 fall_delay &= ~(1 << i);
996 break;
997 }
998 }
999 }
1000
1001 final_fall_delay = get_best_delay(host, fall_delay);
1002
1003skip_fall:
1004 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1005 if (final_maxlen == final_rise_delay.maxlen) {
1006 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1007 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1008 final_rise_delay.final_phase <<
1009 MSDC_PAD_TUNE_CMDRDLY_S);
1010 final_delay = final_rise_delay.final_phase;
1011 } else {
1012 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1013 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1014 final_fall_delay.final_phase <<
1015 MSDC_PAD_TUNE_CMDRDLY_S);
1016 final_delay = final_fall_delay.final_phase;
1017 }
1018
1019 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
1020 goto skip_internal;
1021
1022 for (i = 0; i < PAD_DELAY_MAX; i++) {
1023 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1024 i << MSDC_PAD_TUNE_CMDRRDLY_S);
1025
1026 mmc_send_tuning(mmc, opcode, &cmd_err);
1027 if (!cmd_err)
1028 internal_delay |= (1 << i);
1029 }
1030
1031 dev_err(dev, "Final internal delay: 0x%x\n", internal_delay);
1032
1033 internal_delay_phase = get_best_delay(host, internal_delay);
1034 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1035 internal_delay_phase.final_phase <<
1036 MSDC_PAD_TUNE_CMDRRDLY_S);
1037
1038skip_internal:
1039 dev_err(dev, "Final cmd pad delay: %x\n", final_delay);
1040 return final_delay == 0xff ? -EIO : 0;
1041}
1042
1043static int msdc_tune_data(struct udevice *dev, u32 opcode)
1044{
1045 struct msdc_plat *plat = dev_get_platdata(dev);
1046 struct msdc_host *host = dev_get_priv(dev);
1047 struct mmc *mmc = &plat->mmc;
1048 u32 rise_delay = 0, fall_delay = 0;
1049 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
1050 u8 final_delay, final_maxlen;
1051 void __iomem *tune_reg = &host->base->pad_tune;
1052 int cmd_err;
1053 int i, ret;
1054
1055 if (host->dev_comp->pad_tune0)
1056 tune_reg = &host->base->pad_tune0;
1057
1058 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1059 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1060
1061 for (i = 0; i < PAD_DELAY_MAX; i++) {
1062 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1063 i << MSDC_PAD_TUNE_DATRRDLY_S);
1064
1065 ret = mmc_send_tuning(mmc, opcode, &cmd_err);
1066 if (!ret) {
1067 rise_delay |= (1 << i);
1068 } else if (cmd_err) {
1069 /* in this case, retune response is needed */
1070 ret = msdc_tune_response(dev, opcode);
1071 if (ret)
1072 break;
1073 }
1074 }
1075
1076 final_rise_delay = get_best_delay(host, rise_delay);
1077 if (final_rise_delay.maxlen >= 12 ||
1078 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1079 goto skip_fall;
1080
1081 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1082 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1083
1084 for (i = 0; i < PAD_DELAY_MAX; i++) {
1085 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1086 i << MSDC_PAD_TUNE_DATRRDLY_S);
1087
1088 ret = mmc_send_tuning(mmc, opcode, &cmd_err);
1089 if (!ret) {
1090 fall_delay |= (1 << i);
1091 } else if (cmd_err) {
1092 /* in this case, retune response is needed */
1093 ret = msdc_tune_response(dev, opcode);
1094 if (ret)
1095 break;
1096 }
1097 }
1098
1099 final_fall_delay = get_best_delay(host, fall_delay);
1100
1101skip_fall:
1102 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1103 if (final_maxlen == final_rise_delay.maxlen) {
1104 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1105 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1106 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1107 final_rise_delay.final_phase <<
1108 MSDC_PAD_TUNE_DATRRDLY_S);
1109 final_delay = final_rise_delay.final_phase;
1110 } else {
1111 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1112 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1113 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1114 final_fall_delay.final_phase <<
1115 MSDC_PAD_TUNE_DATRRDLY_S);
1116 final_delay = final_fall_delay.final_phase;
1117 }
1118
1119 if (mmc->selected_mode == MMC_HS_200 ||
1120 mmc->selected_mode == UHS_SDR104)
1121 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATWRDLY_M,
1122 host->hs200_write_int_delay <<
1123 MSDC_PAD_TUNE_DATWRDLY_S);
1124
1125 dev_err(dev, "Final data pad delay: %x\n", final_delay);
1126
1127 return final_delay == 0xff ? -EIO : 0;
1128}
1129
1130static int msdc_execute_tuning(struct udevice *dev, uint opcode)
1131{
1132 struct msdc_plat *plat = dev_get_platdata(dev);
1133 struct msdc_host *host = dev_get_priv(dev);
1134 struct mmc *mmc = &plat->mmc;
1135 int ret;
1136
1137 if (mmc->selected_mode == MMC_HS_400) {
1138 writel(host->hs400_ds_delay, &host->base->pad_ds_tune);
1139 /* for hs400 mode it must be set to 0 */
1140 clrbits_le32(&host->base->patch_bit2, MSDC_PB2_CFGCRCSTS);
1141 host->hs400_mode = true;
1142 }
1143
1144 ret = msdc_tune_response(dev, opcode);
1145 if (ret == -EIO) {
1146 dev_err(dev, "Tune response fail!\n");
1147 return ret;
1148 }
1149
1150 if (!host->hs400_mode) {
1151 ret = msdc_tune_data(dev, opcode);
1152 if (ret == -EIO)
1153 dev_err(dev, "Tune data fail!\n");
1154 }
1155
1156 host->saved_tune_para.iocon = readl(&host->base->msdc_iocon);
1157 host->saved_tune_para.pad_tune = readl(&host->base->pad_tune);
1158
1159 return ret;
1160}
1161#endif
1162
1163static void msdc_init_hw(struct msdc_host *host)
1164{
1165 u32 val;
1166 void __iomem *tune_reg = &host->base->pad_tune;
1167
1168 if (host->dev_comp->pad_tune0)
1169 tune_reg = &host->base->pad_tune0;
1170
1171 /* Configure to MMC/SD mode, clock free running */
1172 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_MODE);
1173
1174 /* Use PIO mode */
1175 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_PIO);
1176
1177 /* Reset */
1178 msdc_reset_hw(host);
1179
1180 /* Enable/disable hw card detection according to fdt option */
1181 if (host->builtin_cd)
1182 clrsetbits_le32(&host->base->msdc_ps,
1183 MSDC_PS_CDDBCE_M,
1184 (DEFAULT_CD_DEBOUNCE << MSDC_PS_CDDBCE_S) |
1185 MSDC_PS_CDEN);
1186 else
1187 clrbits_le32(&host->base->msdc_ps, MSDC_PS_CDEN);
1188
1189 /* Clear all interrupts */
1190 val = readl(&host->base->msdc_int);
1191 writel(val, &host->base->msdc_int);
1192
1193 /* Enable data & cmd interrupts */
1194 writel(DATA_INTS_MASK | CMD_INTS_MASK, &host->base->msdc_inten);
1195
1196 writel(0, tune_reg);
1197 writel(0, &host->base->msdc_iocon);
1198
1199 if (host->r_smpl)
1200 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1201 else
1202 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1203
1204 writel(0x403c0046, &host->base->patch_bit0);
1205 writel(0xffff4089, &host->base->patch_bit1);
1206
1207 if (host->dev_comp->stop_clk_fix)
1208 clrsetbits_le32(&host->base->patch_bit1, MSDC_PB1_STOP_DLY_M,
1209 3 << MSDC_PB1_STOP_DLY_S);
1210
1211 if (host->dev_comp->busy_check)
1212 clrbits_le32(&host->base->patch_bit1, (1 << 7));
1213
1214 setbits_le32(&host->base->emmc50_cfg0, EMMC50_CFG_CFCSTS_SEL);
1215
1216 if (host->dev_comp->async_fifo) {
1217 clrsetbits_le32(&host->base->patch_bit2, MSDC_PB2_RESPWAIT_M,
1218 3 << MSDC_PB2_RESPWAIT_S);
1219
1220 if (host->dev_comp->enhance_rx) {
1221 setbits_le32(&host->base->sdc_adv_cfg0,
1222 SDC_RX_ENHANCE_EN);
1223 } else {
1224 clrsetbits_le32(&host->base->patch_bit2,
1225 MSDC_PB2_RESPSTSENSEL_M,
1226 2 << MSDC_PB2_RESPSTSENSEL_S);
1227 clrsetbits_le32(&host->base->patch_bit2,
1228 MSDC_PB2_CRCSTSENSEL_M,
1229 2 << MSDC_PB2_CRCSTSENSEL_S);
1230 }
1231
1232 /* use async fifo to avoid tune internal delay */
1233 clrbits_le32(&host->base->patch_bit2,
1234 MSDC_PB2_CFGRESP);
1235 clrbits_le32(&host->base->patch_bit2,
1236 MSDC_PB2_CFGCRCSTS);
1237 }
1238
1239 if (host->dev_comp->data_tune) {
1240 setbits_le32(tune_reg,
1241 MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
1242 clrsetbits_le32(&host->base->patch_bit0,
1243 MSDC_INT_DAT_LATCH_CK_SEL_M,
1244 host->latch_ck <<
1245 MSDC_INT_DAT_LATCH_CK_SEL_S);
1246 } else {
1247 /* choose clock tune */
1248 setbits_le32(tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
1249 }
1250
1251 /* Configure to enable SDIO mode otherwise sdio cmd5 won't work */
1252 setbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIO);
1253
1254 /* disable detecting SDIO device interrupt function */
1255 clrbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIOIDE);
1256
1257 /* Configure to default data timeout */
1258 clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
1259 3 << SDC_CFG_DTOC_S);
1260
1261 if (host->dev_comp->stop_clk_fix) {
1262 clrbits_le32(&host->base->sdc_fifo_cfg,
1263 SDC_FIFO_CFG_WRVALIDSEL);
1264 clrbits_le32(&host->base->sdc_fifo_cfg,
1265 SDC_FIFO_CFG_RDVALIDSEL);
1266 }
1267
1268 host->def_tune_para.iocon = readl(&host->base->msdc_iocon);
1269 host->def_tune_para.pad_tune = readl(&host->base->pad_tune);
1270}
1271
1272static void msdc_ungate_clock(struct msdc_host *host)
1273{
1274 clk_enable(&host->src_clk);
1275 clk_enable(&host->h_clk);
Fabien Parent297fa1a2019-03-24 16:46:32 +01001276 if (host->src_clk_cg.dev)
1277 clk_enable(&host->src_clk_cg);
developerdc5a9aa2018-11-15 10:08:04 +08001278}
1279
1280static int msdc_drv_probe(struct udevice *dev)
1281{
1282 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1283 struct msdc_plat *plat = dev_get_platdata(dev);
1284 struct msdc_host *host = dev_get_priv(dev);
1285 struct mmc_config *cfg = &plat->cfg;
1286
1287 cfg->name = dev->name;
1288
1289 host->dev_comp = (struct msdc_compatible *)dev_get_driver_data(dev);
1290
1291 host->src_clk_freq = clk_get_rate(&host->src_clk);
1292
1293 if (host->dev_comp->clk_div_bits == 8)
1294 cfg->f_min = host->src_clk_freq / (4 * 255);
1295 else
1296 cfg->f_min = host->src_clk_freq / (4 * 4095);
1297 cfg->f_max = host->src_clk_freq / 2;
1298
1299 cfg->b_max = 1024;
1300 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1301
1302 host->mmc = &plat->mmc;
1303 host->timeout_ns = 100000000;
1304 host->timeout_clks = 3 * 1048576;
1305
1306#ifdef CONFIG_PINCTRL
1307 pinctrl_select_state(dev, "default");
1308#endif
1309
1310 msdc_ungate_clock(host);
1311 msdc_init_hw(host);
1312
1313 upriv->mmc = &plat->mmc;
1314
1315 return 0;
1316}
1317
1318static int msdc_ofdata_to_platdata(struct udevice *dev)
1319{
1320 struct msdc_plat *plat = dev_get_platdata(dev);
1321 struct msdc_host *host = dev_get_priv(dev);
1322 struct mmc_config *cfg = &plat->cfg;
1323 int ret;
1324
1325 host->base = (void *)dev_read_addr(dev);
1326 if (!host->base)
1327 return -EINVAL;
1328
1329 ret = mmc_of_parse(dev, cfg);
1330 if (ret)
1331 return ret;
1332
1333 ret = clk_get_by_name(dev, "source", &host->src_clk);
1334 if (ret < 0)
1335 return ret;
1336
1337 ret = clk_get_by_name(dev, "hclk", &host->h_clk);
1338 if (ret < 0)
1339 return ret;
1340
Fabien Parent297fa1a2019-03-24 16:46:32 +01001341 clk_get_by_name(dev, "source_cg", &host->src_clk_cg); /* optional */
1342
Fabien Parent8ed608a2019-03-24 16:46:34 +01001343#if CONFIG_IS_ENABLED(DM_GPIO)
developerdc5a9aa2018-11-15 10:08:04 +08001344 gpio_request_by_name(dev, "wp-gpios", 0, &host->gpio_wp, GPIOD_IS_IN);
1345 gpio_request_by_name(dev, "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN);
1346#endif
1347
1348 host->hs400_ds_delay = dev_read_u32_default(dev, "hs400-ds-delay", 0);
1349 host->hs200_cmd_int_delay =
1350 dev_read_u32_default(dev, "cmd_int_delay", 0);
1351 host->hs200_write_int_delay =
1352 dev_read_u32_default(dev, "write_int_delay", 0);
1353 host->latch_ck = dev_read_u32_default(dev, "latch-ck", 0);
1354 host->r_smpl = dev_read_u32_default(dev, "r_smpl", 0);
1355 host->builtin_cd = dev_read_u32_default(dev, "builtin-cd", 0);
1356
1357 return 0;
1358}
1359
1360static int msdc_drv_bind(struct udevice *dev)
1361{
1362 struct msdc_plat *plat = dev_get_platdata(dev);
1363
1364 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1365}
1366
1367static const struct dm_mmc_ops msdc_ops = {
1368 .send_cmd = msdc_ops_send_cmd,
1369 .set_ios = msdc_ops_set_ios,
1370 .get_cd = msdc_ops_get_cd,
1371 .get_wp = msdc_ops_get_wp,
1372#ifdef MMC_SUPPORTS_TUNING
1373 .execute_tuning = msdc_execute_tuning,
1374#endif
1375};
1376
1377static const struct msdc_compatible mt7623_compat = {
1378 .clk_div_bits = 12,
1379 .pad_tune0 = true,
1380 .async_fifo = true,
1381 .data_tune = true,
1382 .busy_check = false,
1383 .stop_clk_fix = false,
1384 .enhance_rx = false
1385};
1386
Fabien Parent1d520a42019-03-24 16:46:33 +01001387static const struct msdc_compatible mt8516_compat = {
1388 .clk_div_bits = 12,
1389 .pad_tune0 = true,
1390 .async_fifo = true,
1391 .data_tune = true,
1392 .busy_check = true,
1393 .stop_clk_fix = true,
1394};
1395
Fabien Parentc7da6982019-08-12 20:26:58 +02001396static const struct msdc_compatible mt8183_compat = {
1397 .clk_div_bits = 12,
1398 .pad_tune0 = true,
1399 .async_fifo = true,
1400 .data_tune = true,
1401 .busy_check = true,
1402 .stop_clk_fix = true,
1403};
1404
developerdc5a9aa2018-11-15 10:08:04 +08001405static const struct udevice_id msdc_ids[] = {
1406 { .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },
Fabien Parent1d520a42019-03-24 16:46:33 +01001407 { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat },
Fabien Parentc7da6982019-08-12 20:26:58 +02001408 { .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat },
developerdc5a9aa2018-11-15 10:08:04 +08001409 {}
1410};
1411
1412U_BOOT_DRIVER(mtk_sd_drv) = {
1413 .name = "mtk_sd",
1414 .id = UCLASS_MMC,
1415 .of_match = msdc_ids,
1416 .ofdata_to_platdata = msdc_ofdata_to_platdata,
1417 .bind = msdc_drv_bind,
1418 .probe = msdc_drv_probe,
1419 .ops = &msdc_ops,
1420 .platdata_auto_alloc_size = sizeof(struct msdc_plat),
1421 .priv_auto_alloc_size = sizeof(struct msdc_host),
1422};