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git01.mediatek.com / filogic / uboot / c220bd9bd2b55c07509aaebd89b258971f974ff9 / . / configs / zynq_cc108_defconfig
blob: 4d914ea725e425b345f9bdb26d981f1b80a8965b [file] [log] [blame]
Michal Simek9e996ec2017-11-02 09:18:42 +0100[diff] [blame]1CONFIG_ARM=y
Trevor Woerner43ec7e02019-05-03 09:41:00 -0400[diff] [blame]2CONFIG_SPL_SYS_DCACHE_OFF=y
Michal Simek9e996ec2017-11-02 09:18:42 +0100[diff] [blame]3CONFIG_ARCH_ZYNQ=y
4CONFIG_SYS_TEXT_BASE=0x4000000
Tom Rinic9285bf2019-04-29 15:54:04 -0400[diff] [blame]5CONFIG_SPL_STACK_R_ADDR=0x200000
Michal Simek040050b2018-03-23 09:34:00 +0100[diff] [blame]6CONFIG_SPL=y
Michal Simeka932ae72018-06-04 08:33:30 +0200[diff] [blame]7CONFIG_DEBUG_UART_BASE=0xe0000000
8CONFIG_DEBUG_UART_CLOCK=50000000
Michal Simek9e996ec2017-11-02 09:18:42 +0100[diff] [blame]9CONFIG_DEBUG_UART=y
Michal Simek8a0e11c2018-01-09 19:31:16 +0100[diff] [blame]10CONFIG_DISTRO_DEFAULTS=y
Tom Rinie478f702019-06-02 08:57:32 -0400[diff] [blame]11CONFIG_SYS_CUSTOM_LDSCRIPT=y
12CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
Michal Simek9e996ec2017-11-02 09:18:42 +0100[diff] [blame]13CONFIG_FIT=y
14CONFIG_FIT_SIGNATURE=y
15CONFIG_FIT_VERBOSE=y
Tom Rinic220bd92019-05-23 07:14:07 -0400[diff] [blame^]16CONFIG_LEGACY_IMAGE_FORMAT=y
Michal Simekc7abf8d2017-12-01 13:50:33 +0100[diff] [blame]17CONFIG_SPL_STACK_R=y
Marek Vasute2542252018-04-07 16:05:27 +0200[diff] [blame]18CONFIG_SPL_SPI_LOAD=y
Michal Simek9e996ec2017-11-02 09:18:42 +0100[diff] [blame]19CONFIG_SYS_PROMPT="Zynq> "
Michal Simek9e996ec2017-11-02 09:18:42 +0100[diff] [blame]20CONFIG_CMD_DFU=y
21# CONFIG_CMD_FLASH is not set
22CONFIG_CMD_GPIO=y
23CONFIG_CMD_MMC=y
24CONFIG_CMD_SF=y
25CONFIG_CMD_USB=y
26# CONFIG_CMD_SETEXPR is not set
27CONFIG_CMD_TFTPPUT=y
Michal Simek9e996ec2017-11-02 09:18:42 +0100[diff] [blame]28CONFIG_CMD_CACHE=y
Michal Simek9e996ec2017-11-02 09:18:42 +0100[diff] [blame]29CONFIG_CMD_EXT4_WRITE=y
Tom Rini74060322018-09-03 15:26:12 -0400[diff] [blame]30CONFIG_DEFAULT_DEVICE_TREE="zynq-cc108"
Michal Simek9e996ec2017-11-02 09:18:42 +0100[diff] [blame]31CONFIG_NET_RANDOM_ETHADDR=y
32CONFIG_SPL_DM_SEQ_ALIAS=y
Michal Simek216f6372017-11-03 15:53:56 +0100[diff] [blame]33CONFIG_FPGA_XILINX=y
Vipul Kumar4a4946b2018-02-16 18:02:51 +0530[diff] [blame]34CONFIG_FPGA_ZYNQPL=y
Michal Simek846d61b2018-01-09 15:27:31 +0100[diff] [blame]35CONFIG_DM_GPIO=y
Michal Simek9e996ec2017-11-02 09:18:42 +0100[diff] [blame]36CONFIG_MMC_SDHCI=y
37CONFIG_MMC_SDHCI_ZYNQ=y
38CONFIG_SPI_FLASH=y
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]39CONFIG_SF_DEFAULT_SPEED=30000000
Michal Simekf26b4c72016-01-25 15:39:26 +0100[diff] [blame]40CONFIG_SPI_FLASH_ISSI=y
Michal Simek9e996ec2017-11-02 09:18:42 +0100[diff] [blame]41CONFIG_SPI_FLASH_MACRONIX=y
42CONFIG_SPI_FLASH_SPANSION=y
43CONFIG_SPI_FLASH_STMICRO=y
44CONFIG_SPI_FLASH_WINBOND=y
Vipul Kumar603ca6d2018-01-24 10:51:30 +0530[diff] [blame]45CONFIG_PHY_MARVELL=y
46CONFIG_PHY_REALTEK=y
47CONFIG_PHY_XILINX=y
Adam Ford53705472018-07-20 23:03:57 -0500[diff] [blame]48CONFIG_MII=y
Michal Simek9e996ec2017-11-02 09:18:42 +0100[diff] [blame]49CONFIG_ZYNQ_GEM=y
50CONFIG_DEBUG_UART_ZYNQ=y
Michal Simek9e996ec2017-11-02 09:18:42 +0100[diff] [blame]51CONFIG_DEBUG_UART_ANNOUNCE=y
Michal Simekab754532017-11-06 09:16:05 +0100[diff] [blame]52CONFIG_ZYNQ_SERIAL=y
Michal Simek9e996ec2017-11-02 09:18:42 +0100[diff] [blame]53CONFIG_ZYNQ_QSPI=y
54CONFIG_USB=y
55CONFIG_USB_EHCI_HCD=y
56CONFIG_USB_ULPI_VIEWPORT=y
57CONFIG_USB_ULPI=y
Michal Simek9e996ec2017-11-02 09:18:42 +0100[diff] [blame]58CONFIG_USB_GADGET=y
59CONFIG_CI_UDC=y
60CONFIG_USB_GADGET_DOWNLOAD=y
Lukasz Majewski3c32b422018-01-29 19:30:18 +0100[diff] [blame]61CONFIG_USB_FUNCTION_THOR=y