Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 1 | /* |
Stefan Roese | 9071a44 | 2013-04-25 23:20:23 +0000 | [diff] [blame] | 2 | * Copyright 2012-2013 Stefan Roese <sr@denx.de> |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 3 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __CONFIG_H |
| 8 | #define __CONFIG_H |
| 9 | |
| 10 | /* |
| 11 | * High Level Configuration Options |
| 12 | * (easy to change) |
| 13 | */ |
| 14 | |
| 15 | #define CONFIG_MPC5200 |
Masahiro Yamada | 608ed2c | 2014-01-16 11:03:07 +0900 | [diff] [blame] | 16 | #define CONFIG_A3M071 /* A3M071 board */ |
Stefan Roese | f22d296 | 2014-11-19 09:37:47 +0100 | [diff] [blame] | 17 | #define CONFIG_DISPLAY_BOARDINFO |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 18 | |
| 19 | #define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */ |
| 20 | |
Stefan Roese | 512da3b | 2013-02-07 02:10:11 +0000 | [diff] [blame] | 21 | #define CONFIG_SPL_TARGET "u-boot-img.bin" |
| 22 | |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 23 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ |
| 24 | |
| 25 | #define CONFIG_MISC_INIT_R |
| 26 | #define CONFIG_SYS_LOWBOOT /* Enable lowboot */ |
| 27 | |
Stefan Roese | 512da3b | 2013-02-07 02:10:11 +0000 | [diff] [blame] | 28 | #ifdef CONFIG_A4M2K |
| 29 | #define CONFIG_HOSTNAME a4m2k |
| 30 | #else |
| 31 | #define CONFIG_HOSTNAME a3m071 |
| 32 | #endif |
| 33 | |
Stefan Roese | 5c1617b | 2013-06-22 16:16:25 +0200 | [diff] [blame] | 34 | #define CONFIG_BOOTCOUNT_LIMIT |
| 35 | |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 36 | /* |
| 37 | * Serial console configuration |
| 38 | */ |
| 39 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ |
| 40 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ |
| 41 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 42 | { 9600, 19200, 38400, 57600, 115200, 230400 } |
| 43 | |
| 44 | /* |
| 45 | * Command line configuration. |
| 46 | */ |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 47 | #define CONFIG_CMD_BSP |
| 48 | #define CONFIG_CMD_CACHE |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 49 | #define CONFIG_CMD_MII |
| 50 | #define CONFIG_CMD_REGINFO |
Stefan Roese | 9071a44 | 2013-04-25 23:20:23 +0000 | [diff] [blame] | 51 | #define CONFIG_CMD_DHCP |
| 52 | #define CONFIG_BOOTP_SEND_HOSTNAME |
| 53 | #define CONFIG_BOOTP_SERVERIP |
| 54 | #define CONFIG_BOOTP_MAY_FAIL |
| 55 | #define CONFIG_BOOTP_BOOTPATH |
| 56 | #define CONFIG_BOOTP_GATEWAY |
| 57 | #define CONFIG_BOOTP_SERVERIP |
| 58 | #define CONFIG_NET_RETRY_COUNT 3 |
| 59 | #define CONFIG_CMD_LINK_LOCAL |
| 60 | #define CONFIG_NETCONSOLE |
| 61 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
| 62 | #define CONFIG_CMD_PING |
| 63 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
| 64 | #define CONFIG_MTD_PARTITIONS /* needed for UBI */ |
| 65 | #define CONFIG_FLASH_CFI_MTD |
| 66 | #define MTDIDS_DEFAULT "nor0=fc000000.flash" |
| 67 | #define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:512k(u-boot)," \ |
Stefan Roese | 5c1617b | 2013-06-22 16:16:25 +0200 | [diff] [blame] | 68 | "128k(env1)," \ |
| 69 | "128k(env2)," \ |
Stefan Roese | 9071a44 | 2013-04-25 23:20:23 +0000 | [diff] [blame] | 70 | "128k(hwinfo)," \ |
| 71 | "1M(nvramsim)," \ |
| 72 | "128k(dtb)," \ |
| 73 | "5M(kernel)," \ |
| 74 | "128k(sysinfo)," \ |
| 75 | "7552k(root)," \ |
| 76 | "4M(app)," \ |
Stefan Roese | 5c1617b | 2013-06-22 16:16:25 +0200 | [diff] [blame] | 77 | "5376k(data)," \ |
| 78 | "8M(install)" |
| 79 | |
Stefan Roese | 9071a44 | 2013-04-25 23:20:23 +0000 | [diff] [blame] | 80 | #define CONFIG_LZO /* needed for UBI */ |
| 81 | #define CONFIG_RBTREE /* needed for UBI */ |
| 82 | #define CONFIG_CMD_MTDPARTS |
| 83 | #define CONFIG_CMD_UBI |
| 84 | #define CONFIG_CMD_UBIFS |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 85 | |
| 86 | /* |
| 87 | * IPB Bus clocking configuration. |
| 88 | */ |
| 89 | #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
| 90 | /* define for 66MHz speed - undef for 33MHz PCI clock speed */ |
Stefan Roese | 512da3b | 2013-02-07 02:10:11 +0000 | [diff] [blame] | 91 | #ifdef CONFIG_A4M2K |
| 92 | #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 |
| 93 | #else |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 94 | #undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 |
Stefan Roese | 512da3b | 2013-02-07 02:10:11 +0000 | [diff] [blame] | 95 | #endif |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 96 | |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 97 | /* maximum size of the flat tree (8K) */ |
| 98 | #define OF_FLAT_TREE_MAX_SIZE 8192 |
| 99 | |
| 100 | #define OF_CPU "PowerPC,5200@0" |
| 101 | #define OF_SOC "soc5200@f0000000" |
| 102 | #define OF_TBCLK (bd->bi_busfreq / 4) |
| 103 | #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" |
| 104 | |
| 105 | /* |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 106 | * NOR flash configuration |
| 107 | */ |
| 108 | #define CONFIG_SYS_FLASH_BASE 0xfc000000 |
Stefan Roese | 512da3b | 2013-02-07 02:10:11 +0000 | [diff] [blame] | 109 | #define CONFIG_SYS_FLASH_SIZE 0x02000000 |
Stefan Roese | 9071a44 | 2013-04-25 23:20:23 +0000 | [diff] [blame] | 110 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000) |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 111 | |
| 112 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 113 | #define CONFIG_SYS_MAX_FLASH_SECT 256 |
| 114 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 |
| 115 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 |
| 116 | #define CONFIG_SYS_FLASH_LOCK_TOUT 5 |
| 117 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 |
| 118 | #define CONFIG_SYS_FLASH_PROTECTION |
| 119 | #define CONFIG_FLASH_CFI_DRIVER |
| 120 | #define CONFIG_SYS_FLASH_CFI |
| 121 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 122 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
Stefan Roese | eba076f | 2013-04-04 03:55:42 +0000 | [diff] [blame] | 123 | #define CONFIG_FLASH_VERIFY |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 124 | |
| 125 | /* |
| 126 | * Environment settings |
| 127 | */ |
| 128 | #define CONFIG_ENV_IS_IN_FLASH |
| 129 | #define CONFIG_ENV_SIZE 0x10000 |
| 130 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
| 131 | #define CONFIG_ENV_OVERWRITE |
Stefan Roese | 9071a44 | 2013-04-25 23:20:23 +0000 | [diff] [blame] | 132 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
| 133 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 134 | |
| 135 | /* |
| 136 | * Memory map |
| 137 | */ |
| 138 | #define CONFIG_SYS_MBAR 0xf0000000 |
| 139 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 140 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 |
| 141 | |
| 142 | /* Use SRAM until RAM will be available */ |
| 143 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
| 144 | #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE |
| 145 | |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 146 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ |
Stefan Roese | 1c41976 | 2013-04-25 23:10:02 +0000 | [diff] [blame] | 147 | GENERATED_GBL_DATA_SIZE) |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 148 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 149 | |
| 150 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
| 151 | |
Stefan Roese | 9071a44 | 2013-04-25 23:20:23 +0000 | [diff] [blame] | 152 | #define CONFIG_SYS_MONITOR_LEN (512 << 10) |
| 153 | #define CONFIG_SYS_MALLOC_LEN (4 << 20) |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 154 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) |
| 155 | |
| 156 | /* |
| 157 | * Ethernet configuration |
| 158 | */ |
| 159 | #define CONFIG_MPC5xxx_FEC |
| 160 | #define CONFIG_MPC5xxx_FEC_MII100 |
Stefan Roese | 512da3b | 2013-02-07 02:10:11 +0000 | [diff] [blame] | 161 | #ifdef CONFIG_A4M2K |
| 162 | #define CONFIG_PHY_ADDR 0x01 |
| 163 | #else |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 164 | #define CONFIG_PHY_ADDR 0x00 |
Stefan Roese | 512da3b | 2013-02-07 02:10:11 +0000 | [diff] [blame] | 165 | #endif |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 166 | |
| 167 | /* |
| 168 | * GPIO configuration |
| 169 | */ |
| 170 | |
| 171 | /* |
| 172 | * GPIO-config depends on failsave-level |
| 173 | * failsave 0 means just MPX-config, no digiboard, no fpga |
| 174 | * 1 means digiboard ok |
| 175 | * 2 means fpga ok |
| 176 | */ |
| 177 | |
Stefan Roese | 512da3b | 2013-02-07 02:10:11 +0000 | [diff] [blame] | 178 | #ifdef CONFIG_A4M2K |
Stefan Roese | 9071a44 | 2013-04-25 23:20:23 +0000 | [diff] [blame] | 179 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C805 |
Stefan Roese | 512da3b | 2013-02-07 02:10:11 +0000 | [diff] [blame] | 180 | #else |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 181 | /* for failsave-level 0 - full failsave */ |
| 182 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C005 |
| 183 | /* for failsave-level 1 - only digiboard ok */ |
Stefan Roese | 9071a44 | 2013-04-25 23:20:23 +0000 | [diff] [blame] | 184 | #define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C065 |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 185 | /* for failsave-level 2 - all ok */ |
Stefan Roese | 9071a44 | 2013-04-25 23:20:23 +0000 | [diff] [blame] | 186 | #define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C065 |
Stefan Roese | 512da3b | 2013-02-07 02:10:11 +0000 | [diff] [blame] | 187 | #endif |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 188 | |
Stefan Roese | 223008d | 2013-02-07 02:10:28 +0000 | [diff] [blame] | 189 | #define CONFIG_WDOG_GPIO_PIN GPIO_WKUP_7 |
| 190 | #if defined(CONFIG_A4M2K) && !defined(CONFIG_SPL_BUILD) |
| 191 | #define CONFIG_HW_WATCHDOG /* Use external HW-Watchdog */ |
| 192 | #endif |
| 193 | |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 194 | /* |
| 195 | * Configuration matrix |
Stefan Roese | 9071a44 | 2013-04-25 23:20:23 +0000 | [diff] [blame] | 196 | * MSB LSB |
Stefan Roese | 512da3b | 2013-02-07 02:10:11 +0000 | [diff] [blame] | 197 | * failsave 0 0x1005C005 00010000000001011100000000000101 ( full failsave ) |
Stefan Roese | 9071a44 | 2013-04-25 23:20:23 +0000 | [diff] [blame] | 198 | * failsave 1 0x1005C065 00010000000001011100000001100101 ( digib.-ver ok ) |
| 199 | * failsave 2 0x1005C065 00010000000001011100000001100101 ( all ok ) |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 200 | * || ||| || | ||| | | | | |
| 201 | * || ||| || | ||| | | | | bit rev name |
| 202 | * ++-+++-++--+---+++-+---+---+---+- 0 31 CS1 |
| 203 | * +-+++-++--+---+++-+---+---+---+- 1 30 LPTZ |
| 204 | * ||| || | ||| | | | | 2 29 ALTs |
| 205 | * +++-++--+---+++-+---+---+---+- 3 28 ALTs |
| 206 | * ++-++--+---+++-+---+---+---+- 4 27 CS7 |
| 207 | * +-++--+---+++-+---+---+---+- 5 26 CS6 |
| 208 | * || | ||| | | | | 6 25 ATA |
| 209 | * ++--+---+++-+---+---+---+- 7 24 ATA |
| 210 | * +--+---+++-+---+---+---+- 8 23 IR_USB_CLK |
| 211 | * | ||| | | | | 9 22 IRDA |
| 212 | * | ||| | | | | 10 21 IRDA |
| 213 | * +---+++-+---+---+---+- 11 20 IRDA |
| 214 | * ||| | | | | 12 19 Ether |
| 215 | * ||| | | | | 13 18 Ether |
| 216 | * ||| | | | | 14 17 Ether |
| 217 | * +++-+---+---+---+- 15 16 Ether |
| 218 | * ++-+---+---+---+- 16 15 PCI_DIS |
| 219 | * +-+---+---+---+- 17 14 USB_SE |
| 220 | * | | | | 18 13 USB |
| 221 | * +---+---+---+- 19 12 USB |
| 222 | * | | | 20 11 PSC3 |
| 223 | * | | | 21 10 PSC3 |
| 224 | * | | | 22 9 PSC3 |
| 225 | * +---+---+- 23 8 PSC3 |
| 226 | * | | 24 7 - |
| 227 | * | | 25 6 PSC2 |
| 228 | * | | 26 5 PSC2 |
| 229 | * +---+- 27 4 PSC2 |
| 230 | * | 28 3 - |
| 231 | * | 29 2 PSC1 |
| 232 | * | 30 1 PSC1 |
| 233 | * +- 31 0 PSC1 |
| 234 | */ |
| 235 | |
| 236 | |
| 237 | /* |
| 238 | * Miscellaneous configurable options |
| 239 | */ |
| 240 | #define CONFIG_SYS_LONGHELP |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 241 | |
| 242 | #define CONFIG_CMDLINE_EDITING |
| 243 | #define CONFIG_SYS_HUSH_PARSER |
| 244 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
| 245 | |
| 246 | #if defined(CONFIG_CMD_KGDB) |
| 247 | #define CONFIG_SYS_CBSIZE 1024 |
| 248 | #else |
| 249 | #define CONFIG_SYS_CBSIZE 256 |
| 250 | #endif |
| 251 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
| 252 | #define CONFIG_SYS_MAXARGS 16 |
| 253 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 254 | |
| 255 | #define CONFIG_SYS_MEMTEST_START 0x00100000 |
| 256 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 |
| 257 | |
| 258 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 |
| 259 | |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 260 | #define CONFIG_LOOPW |
| 261 | #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/ |
| 262 | |
| 263 | /* |
| 264 | * Various low-level settings |
| 265 | */ |
| 266 | #define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI) |
| 267 | #define CONFIG_SYS_HID0_FINAL HID0_ICE |
| 268 | |
| 269 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
| 270 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE |
| 271 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE |
| 272 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE |
Stefan Roese | 512da3b | 2013-02-07 02:10:11 +0000 | [diff] [blame] | 273 | |
| 274 | #ifdef CONFIG_A4M2K |
| 275 | /* external MRAM */ |
| 276 | #define CONFIG_SYS_CS1_START 0xf1000000 |
| 277 | #define CONFIG_SYS_CS1_SIZE (512 << 10) /* 512KiB MRAM */ |
| 278 | #endif |
| 279 | |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 280 | #define CONFIG_SYS_CS2_START 0xe0000000 |
| 281 | #define CONFIG_SYS_CS2_SIZE 0x00100000 |
| 282 | |
Stefan Roese | 512da3b | 2013-02-07 02:10:11 +0000 | [diff] [blame] | 283 | /* FPGA slave io (512kiB / 1MiB) - see ticket #66 */ |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 284 | #define CONFIG_SYS_CS3_START 0xE9000000 |
Stefan Roese | 512da3b | 2013-02-07 02:10:11 +0000 | [diff] [blame] | 285 | #ifdef CONFIG_A4M2K |
| 286 | #define CONFIG_SYS_CS3_SIZE 0x00100000 |
| 287 | #else |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 288 | #define CONFIG_SYS_CS3_SIZE 0x00080000 |
Stefan Roese | 512da3b | 2013-02-07 02:10:11 +0000 | [diff] [blame] | 289 | #endif |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 290 | /* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */ |
| 291 | #define CONFIG_SYS_CS3_CFG 0x0032B900 |
| 292 | |
Stefan Roese | 512da3b | 2013-02-07 02:10:11 +0000 | [diff] [blame] | 293 | #ifndef CONFIG_A4M2K |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 294 | /* Diagnosis Interface - see ticket #63 */ |
| 295 | #define CONFIG_SYS_CS4_START 0xEA000000 |
| 296 | #define CONFIG_SYS_CS4_SIZE 0x00000001 |
| 297 | /* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0002B900 */ |
| 298 | #define CONFIG_SYS_CS4_CFG 0x0002B900 |
Stefan Roese | 512da3b | 2013-02-07 02:10:11 +0000 | [diff] [blame] | 299 | #endif |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 300 | |
Stefan Roese | 512da3b | 2013-02-07 02:10:11 +0000 | [diff] [blame] | 301 | /* FPGA master io (64kiB / 1MiB) - see ticket #66 */ |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 302 | #define CONFIG_SYS_CS5_START 0xE8000000 |
Stefan Roese | 512da3b | 2013-02-07 02:10:11 +0000 | [diff] [blame] | 303 | #ifdef CONFIG_A4M2K |
| 304 | #define CONFIG_SYS_CS5_SIZE 0x00100000 |
| 305 | #else |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 306 | #define CONFIG_SYS_CS5_SIZE 0x00010000 |
Stefan Roese | 512da3b | 2013-02-07 02:10:11 +0000 | [diff] [blame] | 307 | #endif |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 308 | /* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */ |
| 309 | #define CONFIG_SYS_CS5_CFG 0x0032B900 |
| 310 | |
| 311 | #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for pci_clk = 66 MHz */ |
| 312 | #define CONFIG_SYS_BOOTCS_CFG 0x0006F900 |
Stefan Roese | 512da3b | 2013-02-07 02:10:11 +0000 | [diff] [blame] | 313 | #define CONFIG_SYS_CS1_CFG 0x0008FD00 |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 314 | #define CONFIG_SYS_CS2_CFG 0x0006F90C |
| 315 | #else /* for pci_clk = 33 MHz */ |
| 316 | #define CONFIG_SYS_BOOTCS_CFG 0x0002F900 |
| 317 | #define CONFIG_SYS_CS1_CFG 0x0001FB00 |
| 318 | #define CONFIG_SYS_CS2_CFG 0x0002F90C |
| 319 | #endif |
| 320 | |
| 321 | #define CONFIG_SYS_CS_BURST 0x00000000 |
| 322 | /* set DC for FPGA CS5 and CS3 to 0 - see ticket #66 */ |
| 323 | /* R 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 */ |
| 324 | /* 00 11 00 11 00 00 00 11 00 00 00 00 00 00 00 00 */ |
| 325 | #define CONFIG_SYS_CS_DEADCYCLE 0x33030000 |
| 326 | |
| 327 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
| 328 | |
| 329 | /* |
| 330 | * Environment Configuration |
| 331 | */ |
| 332 | |
Stefan Roese | 9071a44 | 2013-04-25 23:20:23 +0000 | [diff] [blame] | 333 | #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 334 | #undef CONFIG_BOOTARGS |
| 335 | #define CONFIG_ZERO_BOOTDELAY_CHECK |
| 336 | |
Stefan Roese | 9071a44 | 2013-04-25 23:20:23 +0000 | [diff] [blame] | 337 | #define CONFIG_SYS_AUTOLOAD "n" |
| 338 | |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 339 | #define CONFIG_PREBOOT "echo;" \ |
| 340 | "echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \ |
| 341 | "echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \ |
| 342 | "echo" |
| 343 | |
| 344 | #undef CONFIG_BOOTARGS |
| 345 | |
Stefan Roese | 9071a44 | 2013-04-25 23:20:23 +0000 | [diff] [blame] | 346 | #define CONFIG_SYS_OS_BASE 0xfc200000 |
| 347 | #define CONFIG_SYS_FDT_BASE 0xfc1e0000 |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 348 | |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 349 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 350 | "netdev=eth0\0" \ |
| 351 | "verify=no\0" \ |
Stefan Roese | 512da3b | 2013-02-07 02:10:11 +0000 | [diff] [blame] | 352 | "loadaddr=200000\0" \ |
| 353 | "kernel_addr=" __stringify(CONFIG_SYS_OS_BASE) "\0" \ |
| 354 | "kernel_addr_r=1000000\0" \ |
| 355 | "fdt_addr=" __stringify(CONFIG_SYS_FDT_BASE) "\0" \ |
| 356 | "fdt_addr_r=1800000\0" \ |
| 357 | "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ |
| 358 | "fdtfile=" __stringify(CONFIG_HOSTNAME) "/" \ |
| 359 | __stringify(CONFIG_HOSTNAME) ".dtb\0" \ |
| 360 | "rootpath=/opt/eldk-5.2.1/powerpc/" \ |
| 361 | "core-image-minimal-mtdutils-dropbear-generic\0" \ |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 362 | "consoledev=ttyPSC0\0" \ |
| 363 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
| 364 | "nfsroot=${serverip}:${rootpath}\0" \ |
| 365 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
Stefan Roese | 5c1617b | 2013-06-22 16:16:25 +0200 | [diff] [blame] | 366 | "mtdargs=setenv bootargs root=/dev/mtdblock8 " \ |
Stefan Roese | 9071a44 | 2013-04-25 23:20:23 +0000 | [diff] [blame] | 367 | "rootfstype=squashfs,jffs2\0" \ |
| 368 | "addhost=setenv bootargs ${bootargs} " \ |
| 369 | "hostname=${hostname}\0" \ |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 370 | "addip=setenv bootargs ${bootargs} " \ |
| 371 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ |
| 372 | ":${hostname}:${netdev}:off panic=1\0" \ |
| 373 | "addtty=setenv bootargs ${bootargs} " \ |
| 374 | "console=${consoledev},${baudrate}\0" \ |
Stefan Roese | 5c1617b | 2013-06-22 16:16:25 +0200 | [diff] [blame] | 375 | "flash_nfs=run nfsargs addip addtty addmtd addhost;" \ |
Stefan Roese | 9071a44 | 2013-04-25 23:20:23 +0000 | [diff] [blame] | 376 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ |
Stefan Roese | 5c1617b | 2013-06-22 16:16:25 +0200 | [diff] [blame] | 377 | "flash_mtd=run mtdargs addip addtty addmtd addhost;" \ |
Stefan Roese | 9071a44 | 2013-04-25 23:20:23 +0000 | [diff] [blame] | 378 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ |
Stefan Roese | 5c1617b | 2013-06-22 16:16:25 +0200 | [diff] [blame] | 379 | "flash_self=run ramargs addip addtty addmtd addhost;" \ |
Stefan Roese | 512da3b | 2013-02-07 02:10:11 +0000 | [diff] [blame] | 380 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ |
| 381 | "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ |
| 382 | "tftp ${fdt_addr_r} ${fdtfile};" \ |
Stefan Roese | 5c1617b | 2013-06-22 16:16:25 +0200 | [diff] [blame] | 383 | "run nfsargs addip addtty addmtd addhost;" \ |
Stefan Roese | 512da3b | 2013-02-07 02:10:11 +0000 | [diff] [blame] | 384 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ |
| 385 | "load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME) \ |
| 386 | "/u-boot-img.bin\0" \ |
Stefan Roese | 5c1617b | 2013-06-22 16:16:25 +0200 | [diff] [blame] | 387 | "update=protect off fc000000 fc07ffff;" \ |
Stefan Roese | 9071a44 | 2013-04-25 23:20:23 +0000 | [diff] [blame] | 388 | "era fc000000 fc07ffff;" \ |
| 389 | "cp.b ${loadaddr} fc000000 ${filesize}\0" \ |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 390 | "upd=run load;run update\0" \ |
Stefan Roese | 5c1617b | 2013-06-22 16:16:25 +0200 | [diff] [blame] | 391 | "upd_fdt=tftp 1800000 a3m071/a3m071.dtb;" \ |
| 392 | "run mtdargs addip addtty addmtd addhost;" \ |
| 393 | "fdt addr 1800000;fdt boardsetup;fdt chosen;" \ |
| 394 | "erase fc1e0000 fc1fffff;cp.b 1800000 fc1e0000 20000" \ |
| 395 | "upd_kernel=tftp 1000000 a3m071/uImage-uncompressed;" \ |
| 396 | "erase fc200000 fc6fffff;" \ |
| 397 | "cp.b 1000000 fc200000 ${filesize}" \ |
| 398 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ |
| 399 | "mtdids=" MTDIDS_DEFAULT "\0" \ |
| 400 | "mtdparts=" MTDPARTS_DEFAULT "\0" \ |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 401 | "" |
| 402 | |
| 403 | #define CONFIG_BOOTCOMMAND "run flash_mtd" |
| 404 | |
| 405 | /* |
| 406 | * SPL related defines |
| 407 | */ |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 408 | #define CONFIG_SPL_FRAMEWORK |
Stefan Roese | 512da3b | 2013-02-07 02:10:11 +0000 | [diff] [blame] | 409 | #define CONFIG_SPL_BOARD_INIT |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 410 | #define CONFIG_SPL_NOR_SUPPORT |
| 411 | #define CONFIG_SPL_TEXT_BASE 0xfc000000 |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 412 | #define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */ |
| 413 | #define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */ |
| 414 | #define CONFIG_SPL_SERIAL_SUPPORT |
| 415 | |
| 416 | /* Place BSS for SPL near end of SDRAM */ |
| 417 | #define CONFIG_SPL_BSS_START_ADDR ((128 - 1) << 20) |
| 418 | #define CONFIG_SPL_BSS_MAX_SIZE (64 << 10) |
| 419 | |
| 420 | #define CONFIG_SPL_OS_BOOT |
Ying Zhang | 602f7d3 | 2013-05-20 14:07:25 +0800 | [diff] [blame] | 421 | #define CONFIG_SPL_ENV_SUPPORT |
Stefan Roese | e1b8d0b | 2012-08-14 15:04:19 +0200 | [diff] [blame] | 422 | /* Place patched DT blob (fdt) at this address */ |
| 423 | #define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000 |
| 424 | |
| 425 | /* Settings for real U-Boot to be loaded from NOR flash */ |
| 426 | #ifndef __ASSEMBLY__ |
| 427 | extern char __spl_flash_end[]; |
| 428 | #endif |
| 429 | #define CONFIG_SYS_UBOOT_BASE __spl_flash_end |
| 430 | #define CONFIG_SYS_SPL_MAX_LEN (32 << 10) |
| 431 | #define CONFIG_SYS_UBOOT_START 0x1000100 |
| 432 | |
| 433 | #endif /* __CONFIG_H */ |