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Tom Rini8b0c8a12018-05-06 18:27:01 -04001/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
Simon Glass07e922a2015-04-28 20:25:10 -06002/*
3 * Copyright(c) 2009 Intel Corporation. All rights reserved.
Simon Glass07e922a2015-04-28 20:25:10 -06004 */
5
6#ifndef _LINUX_SFI_H
7#define _LINUX_SFI_H
8
9#include <errno.h>
10#include <linux/types.h>
11
12/* Table signatures reserved by the SFI specification */
13#define SFI_SIG_SYST "SYST"
14#define SFI_SIG_FREQ "FREQ"
15#define SFI_SIG_CPUS "CPUS"
16#define SFI_SIG_MTMR "MTMR"
17#define SFI_SIG_MRTC "MRTC"
18#define SFI_SIG_MMAP "MMAP"
19#define SFI_SIG_APIC "APIC"
20#define SFI_SIG_XSDT "XSDT"
21#define SFI_SIG_WAKE "WAKE"
22#define SFI_SIG_DEVS "DEVS"
23#define SFI_SIG_GPIO "GPIO"
24
25#define SFI_SIGNATURE_SIZE 4
26#define SFI_OEM_ID_SIZE 6
27#define SFI_OEM_TABLE_ID_SIZE 8
28
29#define SFI_NAME_LEN 16
30#define SFI_TABLE_MAX_ENTRIES 16
31
32#define SFI_GET_NUM_ENTRIES(ptable, entry_type) \
33 ((ptable->header.len - sizeof(struct sfi_table_header)) / \
34 (sizeof(entry_type)))
35/*
36 * Table structures must be byte-packed to match the SFI specification,
37 * as they are provided by the BIOS.
38 */
39struct __packed sfi_table_header {
40 char sig[SFI_SIGNATURE_SIZE];
41 u32 len;
42 u8 rev;
43 u8 csum;
44 char oem_id[SFI_OEM_ID_SIZE];
45 char oem_table_id[SFI_OEM_TABLE_ID_SIZE];
46};
47
48struct __packed sfi_table_simple {
49 struct sfi_table_header header;
50 u64 pentry[1];
51};
52
53/* Comply with UEFI spec 2.1 */
54struct __packed sfi_mem_entry {
55 u32 type;
56 u64 phys_start;
57 u64 virt_start;
58 u64 pages;
59 u64 attrib;
60};
61
Felipe Balbie564d592017-07-06 14:41:52 +030062/* Memory type definitions */
63enum sfi_mem_type {
64 SFI_MEM_RESERVED,
65 SFI_LOADER_CODE,
66 SFI_LOADER_DATA,
67 SFI_BOOT_SERVICE_CODE,
68 SFI_BOOT_SERVICE_DATA,
69 SFI_RUNTIME_SERVICE_CODE,
70 SFI_RUNTIME_SERVICE_DATA,
71 SFI_MEM_CONV,
72 SFI_MEM_UNUSABLE,
73 SFI_ACPI_RECLAIM,
74 SFI_ACPI_NVS,
75 SFI_MEM_MMIO,
76 SFI_MEM_IOPORT,
77 SFI_PAL_CODE,
78 SFI_MEM_TYPEMAX,
79};
80
Simon Glass07e922a2015-04-28 20:25:10 -060081struct __packed sfi_cpu_table_entry {
82 u32 apic_id;
83};
84
85struct __packed sfi_cstate_table_entry {
86 u32 hint; /* MWAIT hint */
87 u32 latency; /* latency in ms */
88};
89
90struct __packed sfi_apic_table_entry {
91 u64 phys_addr; /* phy base addr for APIC reg */
92};
93
94struct __packed sfi_freq_table_entry {
95 u32 freq_mhz; /* in MHZ */
96 u32 latency; /* transition latency in ms */
97 u32 ctrl_val; /* value to write to PERF_CTL */
98};
99
100struct __packed sfi_wake_table_entry {
101 u64 phys_addr; /* pointer to where the wake vector locates */
102};
103
104struct __packed sfi_timer_table_entry {
105 u64 phys_addr; /* phy base addr for the timer */
106 u32 freq_hz; /* in HZ */
107 u32 irq;
108};
109
110struct __packed sfi_rtc_table_entry {
111 u64 phys_addr; /* phy base addr for the RTC */
112 u32 irq;
113};
114
115struct __packed sfi_device_table_entry {
116 u8 type; /* bus type, I2C, SPI or ...*/
117 u8 host_num; /* attached to host 0, 1...*/
118 u16 addr;
119 u8 irq;
120 u32 max_freq;
121 char name[SFI_NAME_LEN];
122};
123
124enum {
125 SFI_DEV_TYPE_SPI = 0,
126 SFI_DEV_TYPE_I2C,
127 SFI_DEV_TYPE_UART,
128 SFI_DEV_TYPE_HSI,
129 SFI_DEV_TYPE_IPC,
130 SFI_DEV_TYPE_SD,
131};
132
133struct __packed sfi_gpio_table_entry {
134 char controller_name[SFI_NAME_LEN];
135 u16 pin_no;
136 char pin_name[SFI_NAME_LEN];
137};
138
139struct sfi_xsdt_header {
140 uint32_t oem_revision;
141 uint32_t creator_id;
142 uint32_t creator_revision;
143};
144
145typedef int (*sfi_table_handler) (struct sfi_table_header *table);
146
147/**
148 * write_sfi_table() - Write Simple Firmware Interface tables
149 *
150 * @base: Address to write table to
151 * @return address to use for the next table
152 */
Simon Glassca37a392017-01-16 07:03:35 -0700153ulong write_sfi_table(ulong base);
Simon Glass07e922a2015-04-28 20:25:10 -0600154
155#endif /*_LINUX_SFI_H */