| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/iommu/rockchip,iommu.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Rockchip IOMMU |
| 8 | |
| 9 | maintainers: |
| 10 | - Heiko Stuebner <heiko@sntech.de> |
| 11 | |
| 12 | description: |+ |
| 13 | A Rockchip DRM iommu translates io virtual addresses to physical addresses for |
| 14 | its master device. Each slave device is bound to a single master device and |
| 15 | shares its clocks, power domain and irq. |
| 16 | |
| 17 | For information on assigning IOMMU controller to its peripheral devices, |
| 18 | see generic IOMMU bindings. |
| 19 | |
| 20 | properties: |
| 21 | compatible: |
| 22 | enum: |
| 23 | - rockchip,iommu |
| 24 | - rockchip,rk3568-iommu |
| 25 | |
| 26 | reg: |
| 27 | items: |
| 28 | - description: configuration registers for MMU instance 0 |
| 29 | - description: configuration registers for MMU instance 1 |
| 30 | minItems: 1 |
| 31 | |
| 32 | interrupts: |
| 33 | items: |
| 34 | - description: interruption for MMU instance 0 |
| 35 | - description: interruption for MMU instance 1 |
| 36 | minItems: 1 |
| 37 | |
| 38 | clocks: |
| 39 | items: |
| 40 | - description: Core clock |
| 41 | - description: Interface clock |
| 42 | |
| 43 | clock-names: |
| 44 | items: |
| 45 | - const: aclk |
| 46 | - const: iface |
| 47 | |
| 48 | "#iommu-cells": |
| 49 | const: 0 |
| 50 | |
| 51 | power-domains: |
| 52 | maxItems: 1 |
| 53 | |
| 54 | rockchip,disable-mmu-reset: |
| 55 | $ref: /schemas/types.yaml#/definitions/flag |
| 56 | description: | |
| 57 | Do not use the mmu reset operation. |
| 58 | Some mmu instances may produce unexpected results |
| 59 | when the reset operation is used. |
| 60 | |
| 61 | required: |
| 62 | - compatible |
| 63 | - reg |
| 64 | - interrupts |
| 65 | - clocks |
| 66 | - clock-names |
| 67 | - "#iommu-cells" |
| 68 | |
| 69 | additionalProperties: false |
| 70 | |
| 71 | examples: |
| 72 | - | |
| 73 | #include <dt-bindings/clock/rk3399-cru.h> |
| 74 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 75 | |
| 76 | vopl_mmu: iommu@ff940300 { |
| 77 | compatible = "rockchip,iommu"; |
| 78 | reg = <0xff940300 0x100>; |
| 79 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
| 80 | clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; |
| 81 | clock-names = "aclk", "iface"; |
| 82 | #iommu-cells = <0>; |
| 83 | }; |