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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Paul Thacker1dc42832016-01-28 15:30:14 +05302/*
3 * (c) 2015 Paul Thacker <paul.thacker@microchip.com>
4 *
Paul Thacker1dc42832016-01-28 15:30:14 +05305 */
6#include <common.h>
7#include <clk.h>
8#include <dm.h>
Simon Glass9bc15642020-02-03 07:36:16 -07009#include <malloc.h>
Paul Thacker1dc42832016-01-28 15:30:14 +053010#include <serial.h>
11#include <wait_bit.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060012#include <linux/bitops.h>
Paul Thacker1dc42832016-01-28 15:30:14 +053013#include <mach/pic32.h>
14#include <dt-bindings/clock/microchip,clock.h>
15
16DECLARE_GLOBAL_DATA_PTR;
17
18/* UART Control Registers */
19#define U_MOD 0x00
20#define U_MODCLR (U_MOD + _CLR_OFFSET)
21#define U_MODSET (U_MOD + _SET_OFFSET)
22#define U_STA 0x10
23#define U_STACLR (U_STA + _CLR_OFFSET)
24#define U_STASET (U_STA + _SET_OFFSET)
25#define U_TXR 0x20
26#define U_RXR 0x30
27#define U_BRG 0x40
28
29/* U_MOD bits */
30#define UART_ENABLE BIT(15)
31
32/* U_STA bits */
33#define UART_RX_ENABLE BIT(12)
34#define UART_TX_BRK BIT(11)
35#define UART_TX_ENABLE BIT(10)
36#define UART_TX_FULL BIT(9)
37#define UART_TX_EMPTY BIT(8)
38#define UART_RX_OVER BIT(1)
39#define UART_RX_DATA_AVAIL BIT(0)
40
41struct pic32_uart_priv {
42 void __iomem *base;
43 ulong uartclk;
44};
45
46/*
47 * Initialize the serial port with the given baudrate.
48 * The settings are always 8 data bits, no parity, 1 stop bit, no start bits.
49 */
50static int pic32_serial_init(void __iomem *base, ulong clk, u32 baudrate)
51{
52 u32 div = DIV_ROUND_CLOSEST(clk, baudrate * 16);
53
54 /* wait for TX FIFO to empty */
Álvaro Fernández Rojas918de032018-01-23 17:14:55 +010055 wait_for_bit_le32(base + U_STA, UART_TX_EMPTY,
56 true, CONFIG_SYS_HZ, false);
Paul Thacker1dc42832016-01-28 15:30:14 +053057
58 /* send break */
59 writel(UART_TX_BRK, base + U_STASET);
60
61 /* disable and clear mode */
62 writel(0, base + U_MOD);
63 writel(0, base + U_STA);
64
65 /* set baud rate generator */
66 writel(div - 1, base + U_BRG);
67
68 /* enable the UART for TX and RX */
69 writel(UART_TX_ENABLE | UART_RX_ENABLE, base + U_STASET);
70
71 /* enable the UART */
72 writel(UART_ENABLE, base + U_MODSET);
73 return 0;
74}
75
76/* Check whether any char pending in RX fifo */
77static int pic32_uart_pending_input(void __iomem *base)
78{
79 /* check if rx buffer overrun error has occurred */
80 if (readl(base + U_STA) & UART_RX_OVER) {
81 readl(base + U_RXR);
82
83 /* clear overrun error to keep receiving */
84 writel(UART_RX_OVER, base + U_STACLR);
85 }
86
87 /* In PIC32 there is no way to know number of outstanding
88 * chars in rx-fifo. Only it can be known whether there is any.
89 */
90 return readl(base + U_STA) & UART_RX_DATA_AVAIL;
91}
92
93static int pic32_uart_pending(struct udevice *dev, bool input)
94{
95 struct pic32_uart_priv *priv = dev_get_priv(dev);
96
97 if (input)
98 return pic32_uart_pending_input(priv->base);
99
100 return !(readl(priv->base + U_STA) & UART_TX_EMPTY);
101}
102
103static int pic32_uart_setbrg(struct udevice *dev, int baudrate)
104{
105 struct pic32_uart_priv *priv = dev_get_priv(dev);
106
107 return pic32_serial_init(priv->base, priv->uartclk, baudrate);
108}
109
110static int pic32_uart_putc(struct udevice *dev, const char ch)
111{
112 struct pic32_uart_priv *priv = dev_get_priv(dev);
113
114 /* Check if Tx FIFO is full */
115 if (readl(priv->base + U_STA) & UART_TX_FULL)
116 return -EAGAIN;
117
118 /* pump the char to tx buffer */
119 writel(ch, priv->base + U_TXR);
120
121 return 0;
122}
123
124static int pic32_uart_getc(struct udevice *dev)
125{
126 struct pic32_uart_priv *priv = dev_get_priv(dev);
127
128 /* return error if RX fifo is empty */
129 if (!pic32_uart_pending_input(priv->base))
130 return -EAGAIN;
131
132 /* read the character from rx buffer */
133 return readl(priv->base + U_RXR) & 0xff;
134}
135
136static int pic32_uart_probe(struct udevice *dev)
137{
138 struct pic32_uart_priv *priv = dev_get_priv(dev);
Stephen Warrena9622432016-06-17 09:44:00 -0600139 struct clk clk;
Paul Thacker1dc42832016-01-28 15:30:14 +0530140 fdt_addr_t addr;
141 fdt_size_t size;
142 int ret;
143
144 /* get address */
Simon Glassdd79d6e2017-01-17 16:52:55 -0700145 addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
146 &size);
Paul Thacker1dc42832016-01-28 15:30:14 +0530147 if (addr == FDT_ADDR_T_NONE)
148 return -EINVAL;
149
150 priv->base = ioremap(addr, size);
151
152 /* get clock rate */
Stephen Warrena9622432016-06-17 09:44:00 -0600153 ret = clk_get_by_index(dev, 0, &clk);
Paul Thacker1dc42832016-01-28 15:30:14 +0530154 if (ret < 0)
155 return ret;
Stephen Warrena9622432016-06-17 09:44:00 -0600156 priv->uartclk = clk_get_rate(&clk);
157 clk_free(&clk);
Paul Thacker1dc42832016-01-28 15:30:14 +0530158
159 /* initialize serial */
160 return pic32_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE);
161}
162
163static const struct dm_serial_ops pic32_uart_ops = {
164 .putc = pic32_uart_putc,
165 .pending = pic32_uart_pending,
166 .getc = pic32_uart_getc,
167 .setbrg = pic32_uart_setbrg,
168};
169
170static const struct udevice_id pic32_uart_ids[] = {
171 { .compatible = "microchip,pic32mzda-uart" },
172 {}
173};
174
175U_BOOT_DRIVER(pic32_serial) = {
176 .name = "pic32-uart",
177 .id = UCLASS_SERIAL,
178 .of_match = pic32_uart_ids,
179 .probe = pic32_uart_probe,
180 .ops = &pic32_uart_ops,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700181 .priv_auto = sizeof(struct pic32_uart_priv),
Paul Thacker1dc42832016-01-28 15:30:14 +0530182};
183
184#ifdef CONFIG_DEBUG_UART_PIC32
185#include <debug_uart.h>
186
187static inline void _debug_uart_init(void)
188{
189 void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
190
191 pic32_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
192}
193
194static inline void _debug_uart_putc(int ch)
195{
196 writel(ch, CONFIG_DEBUG_UART_BASE + U_TXR);
197}
198
199DEBUG_UART_FUNCS
200#endif