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Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -05001/*
2 * pci.c -- WindRiver SBC8349 PCI board support.
3 * Copyright (c) 2006 Wind River Systems, Inc.
Kim Phillips57a2af32009-07-18 18:42:13 -05004 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -05005 *
6 * Based on MPC8349 PCI support but w/o PIB related code.
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -05009 */
10
11#include <asm/mmu.h>
Kim Phillips57a2af32009-07-18 18:42:13 -050012#include <asm/io.h>
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050013#include <common.h>
Kim Phillips57a2af32009-07-18 18:42:13 -050014#include <mpc83xx.h>
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050015#include <pci.h>
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050016#include <i2c.h>
Kim Phillips57a2af32009-07-18 18:42:13 -050017#include <asm/fsl_i2c.h>
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050018
19DECLARE_GLOBAL_DATA_PTR;
20
Kim Phillips57a2af32009-07-18 18:42:13 -050021static struct pci_region pci1_regions[] = {
22 {
23 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
24 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
25 size: CONFIG_SYS_PCI1_MEM_SIZE,
26 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050027 },
Kim Phillips57a2af32009-07-18 18:42:13 -050028 {
29 bus_start: CONFIG_SYS_PCI1_IO_BASE,
30 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
31 size: CONFIG_SYS_PCI1_IO_SIZE,
32 flags: PCI_REGION_IO
33 },
34 {
35 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
36 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
37 size: CONFIG_SYS_PCI1_MMIO_SIZE,
38 flags: PCI_REGION_MEM
39 },
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050040};
41
Kim Phillips57a2af32009-07-18 18:42:13 -050042/*
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050043 * pci_init_board()
44 *
45 * NOTICE: PCI2 is not supported. There is only one
46 * physical PCI slot on the board.
47 *
48 */
49void
50pci_init_board(void)
51{
Kim Phillips57a2af32009-07-18 18:42:13 -050052 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
53 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
54 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
55 struct pci_region *reg[] = { pci1_regions };
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050056
Kim Phillips57a2af32009-07-18 18:42:13 -050057 /* Enable all 8 PCI_CLK_OUTPUTS */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050058 clk->occr = 0xff000000;
59 udelay(2000);
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050060
Kim Phillips57a2af32009-07-18 18:42:13 -050061 /* Configure PCI Local Access Windows */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020062 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050063 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
64
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020065 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050066 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
67
Kim Phillips57a2af32009-07-18 18:42:13 -050068 udelay(2000);
Kim Phillipsfd47a742007-12-20 14:09:22 -060069
Peter Tysere2283322010-09-14 19:13:50 -050070 mpc83xx_pci_init(1, reg);
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050071}