blob: f2b4177082c41f626ae958edc280057e683941f7 [file] [log] [blame]
Stefan Roese5ffceb82015-03-26 15:36:56 +01001/*
2 * Copyright (C) Marvell International Ltd. and its affiliates
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7#ifndef _DDR3_TRAINING_LEVELING_H_
8#define _DDR3_TRAINING_LEVELING_H_
9
10#define MAX_DQ_READ_LEVELING_DELAY 15
11
12int ddr3_tip_print_wl_supp_result(u32 dev_num);
13int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs,
14 u32 *cs_mask);
15u32 hws_ddr3_tip_max_cs_get(void);
16
17#endif /* _DDR3_TRAINING_LEVELING_H_ */