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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Philipp Tomsich02a61b72017-07-28 17:43:19 +02002/*
3 * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
Philipp Tomsich02a61b72017-07-28 17:43:19 +02004 */
5
6#include <common.h>
Simon Glass1ea97892020-05-10 11:40:00 -06007#include <bootstage.h>
Philipp Tomsich02a61b72017-07-28 17:43:19 +02008#include <dm.h>
Simon Glass97589732020-05-10 11:40:02 -06009#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060011#include <asm/global_data.h>
Philipp Tomsichaad4d572017-09-11 22:04:16 +020012#include <dm/ofnode.h>
Philipp Tomsich02a61b72017-07-28 17:43:19 +020013#include <mapmem.h>
Kever Yang9fbe17c2019-03-28 11:01:23 +080014#include <asm/arch-rockchip/timer.h>
Philipp Tomsich02a61b72017-07-28 17:43:19 +020015#include <dt-structs.h>
16#include <timer.h>
17#include <asm/io.h>
18
19DECLARE_GLOBAL_DATA_PTR;
20
21#if CONFIG_IS_ENABLED(OF_PLATDATA)
22struct rockchip_timer_plat {
23 struct dtd_rockchip_rk3368_timer dtd;
24};
25#endif
26
27/* Driver private data. Contains timer id. Could be either 0 or 1. */
28struct rockchip_timer_priv {
29 struct rk_timer *timer;
30};
31
Philipp Tomsichaad4d572017-09-11 22:04:16 +020032static inline int64_t rockchip_timer_get_curr_value(struct rk_timer *timer)
Philipp Tomsich02a61b72017-07-28 17:43:19 +020033{
Philipp Tomsich02a61b72017-07-28 17:43:19 +020034 uint64_t timebase_h, timebase_l;
35 uint64_t cntr;
36
Philipp Tomsichaad4d572017-09-11 22:04:16 +020037 timebase_l = readl(&timer->timer_curr_value0);
38 timebase_h = readl(&timer->timer_curr_value1);
Philipp Tomsich02a61b72017-07-28 17:43:19 +020039
Philipp Tomsich02a61b72017-07-28 17:43:19 +020040 cntr = timebase_h << 32 | timebase_l;
Philipp Tomsichaad4d572017-09-11 22:04:16 +020041 return cntr;
42}
43
44#if CONFIG_IS_ENABLED(BOOTSTAGE)
45ulong timer_get_boot_us(void)
46{
47 uint64_t ticks = 0;
48 uint32_t rate;
49 uint64_t us;
50 int ret;
51
52 ret = dm_timer_init();
53
54 if (!ret) {
55 /* The timer is available */
56 rate = timer_get_rate(gd->timer);
57 timer_get_count(gd->timer, &ticks);
Simon Glass6d70ba02021-08-07 07:24:06 -060058 } else if (CONFIG_IS_ENABLED(OF_REAL) && ret == -EAGAIN) {
Philipp Tomsichaad4d572017-09-11 22:04:16 +020059 /* We have been called so early that the DM is not ready,... */
60 ofnode node = offset_to_ofnode(-1);
61 struct rk_timer *timer = NULL;
62
63 /*
64 * ... so we try to access the raw timer, if it is specified
65 * via the tick-timer property in /chosen.
66 */
67 node = ofnode_get_chosen_node("tick-timer");
68 if (!ofnode_valid(node)) {
69 debug("%s: no /chosen/tick-timer\n", __func__);
70 return 0;
71 }
72
73 timer = (struct rk_timer *)ofnode_get_addr(node);
74
75 /* This timer is down-counting */
76 ticks = ~0uLL - rockchip_timer_get_curr_value(timer);
77 if (ofnode_read_u32(node, "clock-frequency", &rate)) {
78 debug("%s: could not read clock-frequency\n", __func__);
79 return 0;
80 }
Philipp Tomsichaad4d572017-09-11 22:04:16 +020081 } else {
82 return 0;
83 }
84
85 us = (ticks * 1000) / rate;
86 return us;
87}
88#endif
89
Sean Anderson947fc2d2020-10-07 14:37:44 -040090static u64 rockchip_timer_get_count(struct udevice *dev)
Philipp Tomsichaad4d572017-09-11 22:04:16 +020091{
92 struct rockchip_timer_priv *priv = dev_get_priv(dev);
93 uint64_t cntr = rockchip_timer_get_curr_value(priv->timer);
94
95 /* timers are down-counting */
Sean Anderson947fc2d2020-10-07 14:37:44 -040096 return ~0ull - cntr;
Philipp Tomsich02a61b72017-07-28 17:43:19 +020097}
98
Simon Glassaad29ae2020-12-03 16:55:21 -070099static int rockchip_clk_of_to_plat(struct udevice *dev)
Philipp Tomsich02a61b72017-07-28 17:43:19 +0200100{
Simon Glass6d70ba02021-08-07 07:24:06 -0600101 if (CONFIG_IS_ENABLED(OF_REAL)) {
102 struct rockchip_timer_priv *priv = dev_get_priv(dev);
Philipp Tomsich02a61b72017-07-28 17:43:19 +0200103
Simon Glass6d70ba02021-08-07 07:24:06 -0600104 priv->timer = dev_read_addr_ptr(dev);
105 if (!priv->timer)
106 return -ENOENT;
107 }
Philipp Tomsich02a61b72017-07-28 17:43:19 +0200108
109 return 0;
110}
111
112static int rockchip_timer_start(struct udevice *dev)
113{
114 struct rockchip_timer_priv *priv = dev_get_priv(dev);
115 const uint64_t reload_val = ~0uLL;
116 const uint32_t reload_val_l = reload_val & 0xffffffff;
117 const uint32_t reload_val_h = reload_val >> 32;
118
Philipp Tomsichaad4d572017-09-11 22:04:16 +0200119 /* don't reinit, if the timer is already running and set up */
120 if ((readl(&priv->timer->timer_ctrl_reg) & 1) == 1 &&
121 (readl(&priv->timer->timer_load_count0) == reload_val_l) &&
122 (readl(&priv->timer->timer_load_count1) == reload_val_h))
123 return 0;
124
Philipp Tomsich02a61b72017-07-28 17:43:19 +0200125 /* disable timer and reset all control */
126 writel(0, &priv->timer->timer_ctrl_reg);
127 /* write reload value */
128 writel(reload_val_l, &priv->timer->timer_load_count0);
129 writel(reload_val_h, &priv->timer->timer_load_count1);
130 /* enable timer */
131 writel(1, &priv->timer->timer_ctrl_reg);
132
133 return 0;
134}
135
136static int rockchip_timer_probe(struct udevice *dev)
137{
138#if CONFIG_IS_ENABLED(OF_PLATDATA)
139 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
140 struct rockchip_timer_priv *priv = dev_get_priv(dev);
Simon Glassfa20e932020-12-03 16:55:20 -0700141 struct rockchip_timer_plat *plat = dev_get_plat(dev);
Philipp Tomsich02a61b72017-07-28 17:43:19 +0200142
Philipp Tomsich2924a362017-08-14 19:05:31 +0200143 priv->timer = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
Philipp Tomsich02a61b72017-07-28 17:43:19 +0200144 uc_priv->clock_rate = plat->dtd.clock_frequency;
145#endif
146
147 return rockchip_timer_start(dev);
148}
149
150static const struct timer_ops rockchip_timer_ops = {
151 .get_count = rockchip_timer_get_count,
152};
153
154static const struct udevice_id rockchip_timer_ids[] = {
Philipp Tomsich84e01142018-04-25 14:07:06 +0200155 { .compatible = "rockchip,rk3188-timer" },
156 { .compatible = "rockchip,rk3288-timer" },
Philipp Tomsich02a61b72017-07-28 17:43:19 +0200157 { .compatible = "rockchip,rk3368-timer" },
158 {}
159};
160
Philipp Tomsich9b32b572017-08-25 13:22:00 +0200161U_BOOT_DRIVER(rockchip_rk3368_timer) = {
Philipp Tomsich02a61b72017-07-28 17:43:19 +0200162 .name = "rockchip_rk3368_timer",
163 .id = UCLASS_TIMER,
164 .of_match = rockchip_timer_ids,
165 .probe = rockchip_timer_probe,
166 .ops = &rockchip_timer_ops,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700167 .priv_auto = sizeof(struct rockchip_timer_priv),
Philipp Tomsich02a61b72017-07-28 17:43:19 +0200168#if CONFIG_IS_ENABLED(OF_PLATDATA)
Simon Glass71fa5b42020-12-03 16:55:18 -0700169 .plat_auto = sizeof(struct rockchip_timer_plat),
Philipp Tomsich02a61b72017-07-28 17:43:19 +0200170#endif
Simon Glassaad29ae2020-12-03 16:55:21 -0700171 .of_to_plat = rockchip_clk_of_to_plat,
Philipp Tomsich02a61b72017-07-28 17:43:19 +0200172};