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git01.mediatek.com / filogic / uboot / c0bc2e1a35450a3d034700b8c35243502670542d / . / include / ppc405.h
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wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]1/*----------------------------------------------------------------------------+
2|
3| This source code has been made available to you by IBM on an AS-IS
4| basis. Anyone receiving this source is licensed under IBM
5| copyrights to use it in any way he or she deems fit, including
6| copying it, modifying it, compiling it, and redistributing it either
7| with or without modifications. No license under IBM patents or
8| patent applications is to be implied by the copyright license.
9|
10| Any user of this software should understand that IBM cannot provide
11| technical support for this software and will not be responsible for
12| any consequences resulting from the use of this software.
13|
14| Any person who transfers this source code or any derivative work
15| must include the IBM copyright notice, this paragraph, and the
16| preceding two paragraphs in the transferred software.
17|
18| COPYRIGHT I B M CORPORATION 1999
19| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20+----------------------------------------------------------------------------*/
21
22#ifndef __PPC405_H__
23#define __PPC405_H__
24
25/*--------------------------------------------------------------------- */
26/* Special Purpose Registers */
27/*--------------------------------------------------------------------- */
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]28 #define srr2 0x3de /* save/restore register 2 */
29 #define srr3 0x3df /* save/restore register 3 */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]30 #define dbsr 0x3f0 /* debug status register */
31 #define dbcr0 0x3f2 /* debug control register 0 */
32 #define dbcr1 0x3bd /* debug control register 1 */
33 #define iac1 0x3f4 /* instruction address comparator 1 */
34 #define iac2 0x3f5 /* instruction address comparator 2 */
35 #define iac3 0x3b4 /* instruction address comparator 3 */
36 #define iac4 0x3b5 /* instruction address comparator 4 */
37 #define dac1 0x3f6 /* data address comparator 1 */
38 #define dac2 0x3f7 /* data address comparator 2 */
39 #define dccr 0x3fa /* data cache control register */
40 #define iccr 0x3fb /* instruction cache control register */
41 #define esr 0x3d4 /* execption syndrome register */
42 #define dear 0x3d5 /* data exeption address register */
43 #define evpr 0x3d6 /* exeption vector prefix register */
44 #define tsr 0x3d8 /* timer status register */
45 #define tcr 0x3da /* timer control register */
46 #define pit 0x3db /* programmable interval timer */
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]47 #define sgr 0x3b9 /* storage guarded reg */
48 #define dcwr 0x3ba /* data cache write-thru reg*/
49 #define sler 0x3bb /* storage little-endian reg */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]50 #define cdbcr 0x3d7 /* cache debug cntrl reg */
51 #define icdbdr 0x3d3 /* instr cache dbug data reg*/
52 #define ccr0 0x3b3 /* core configuration register */
53 #define dvc1 0x3b6 /* data value compare register 1 */
54 #define dvc2 0x3b7 /* data value compare register 2 */
55 #define pid 0x3b1 /* process ID */
56 #define su0r 0x3bc /* storage user-defined register 0 */
57 #define zpr 0x3b0 /* zone protection regsiter */
58
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]59 #define tbl 0x11c /* time base lower - privileged write */
60 #define tbu 0x11d /* time base upper - privileged write */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]61
62 #define sprg4r 0x104 /* Special purpose general 4 - read only */
63 #define sprg5r 0x105 /* Special purpose general 5 - read only */
64 #define sprg6r 0x106 /* Special purpose general 6 - read only */
65 #define sprg7r 0x107 /* Special purpose general 7 - read only */
66 #define sprg4w 0x114 /* Special purpose general 4 - write only */
67 #define sprg5w 0x115 /* Special purpose general 5 - write only */
68 #define sprg6w 0x116 /* Special purpose general 6 - write only */
69 #define sprg7w 0x117 /* Special purpose general 7 - write only */
70
71/******************************************************************************
72 * Special for PPC405GP
73 ******************************************************************************/
74
75/******************************************************************************
76 * DMA
77 ******************************************************************************/
78#define DMA_DCR_BASE 0x100
79#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
80#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
81#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */
82#define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */
83#define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */
84#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
85#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
86#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */
87#define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */
88#define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */
89#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
90#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
91#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */
92#define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */
93#define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */
94#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */
95#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */
96#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */
97#define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */
98#define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */
99#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
100#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
101#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */
102
103/******************************************************************************
104 * Universal interrupt controller
105 ******************************************************************************/
106#define UIC_DCR_BASE 0xc0
107#define uicsr (UIC_DCR_BASE+0x0) /* UIC status */
108#define uicsrs (UIC_DCR_BASE+0x1) /* UIC status set */
109#define uicer (UIC_DCR_BASE+0x2) /* UIC enable */
110#define uiccr (UIC_DCR_BASE+0x3) /* UIC critical */
111#define uicpr (UIC_DCR_BASE+0x4) /* UIC polarity */
112#define uictr (UIC_DCR_BASE+0x5) /* UIC triggering */
113#define uicmsr (UIC_DCR_BASE+0x6) /* UIC masked status */
114#define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */
115#define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */
116
117/*-----------------------------------------------------------------------------+
118| Universal interrupt controller interrupts
119+-----------------------------------------------------------------------------*/
120#define UIC_UART0 0x80000000 /* UART 0 */
121#define UIC_UART1 0x40000000 /* UART 1 */
122#define UIC_IIC 0x20000000 /* IIC */
123#define UIC_EXT_MAST 0x10000000 /* External Master */
124#define UIC_PCI 0x08000000 /* PCI write to command reg */
125#define UIC_DMA0 0x04000000 /* DMA chan. 0 */
126#define UIC_DMA1 0x02000000 /* DMA chan. 1 */
127#define UIC_DMA2 0x01000000 /* DMA chan. 2 */
128#define UIC_DMA3 0x00800000 /* DMA chan. 3 */
129#define UIC_EMAC_WAKE 0x00400000 /* EMAC wake up */
130#define UIC_MAL_SERR 0x00200000 /* MAL SERR */
131#define UIC_MAL_TXEOB 0x00100000 /* MAL TXEOB */
132#define UIC_MAL_RXEOB 0x00080000 /* MAL RXEOB */
133#define UIC_MAL_TXDE 0x00040000 /* MAL TXDE */
134#define UIC_MAL_RXDE 0x00020000 /* MAL RXDE */
135#define UIC_ENET 0x00010000 /* Ethernet */
136#define UIC_EXT_PCI_SERR 0x00008000 /* External PCI SERR# */
137#define UIC_ECC_CE 0x00004000 /* ECC Correctable Error */
138#define UIC_PCI_PM 0x00002000 /* PCI Power Management */
139#define UIC_EXT0 0x00000040 /* External interrupt 0 */
140#define UIC_EXT1 0x00000020 /* External interrupt 1 */
141#define UIC_EXT2 0x00000010 /* External interrupt 2 */
142#define UIC_EXT3 0x00000008 /* External interrupt 3 */
143#define UIC_EXT4 0x00000004 /* External interrupt 4 */
144#define UIC_EXT5 0x00000002 /* External interrupt 5 */
145#define UIC_EXT6 0x00000001 /* External interrupt 6 */
146
147/******************************************************************************
148 * SDRAM Controller
149 ******************************************************************************/
150#define SDRAM_DCR_BASE 0x10
151#define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */
152#define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */
153 /* values for memcfga register - indirect addressing of these regs */
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]154#ifndef CONFIG_405EP
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]155 #define mem_besra 0x00 /* bus error syndrome reg a */
156 #define mem_besrsa 0x04 /* bus error syndrome reg set a */
157 #define mem_besrb 0x08 /* bus error syndrome reg b */
158 #define mem_besrsb 0x0c /* bus error syndrome reg set b */
159 #define mem_bear 0x10 /* bus error address reg */
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]160#endif
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]161 #define mem_mcopt1 0x20 /* memory controller options 1 */
162 #define mem_rtr 0x30 /* refresh timer reg */
163 #define mem_pmit 0x34 /* power management idle timer */
164 #define mem_mb0cf 0x40 /* memory bank 0 configuration */
165 #define mem_mb1cf 0x44 /* memory bank 1 configuration */
stroeseb0ca12d2003-12-09 14:59:11 +0000[diff] [blame]166#ifndef CONFIG_405EP
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]167 #define mem_mb2cf 0x48 /* memory bank 2 configuration */
168 #define mem_mb3cf 0x4c /* memory bank 3 configuration */
stroeseb0ca12d2003-12-09 14:59:11 +0000[diff] [blame]169#endif
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]170 #define mem_sdtr1 0x80 /* timing reg 1 */
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]171#ifndef CONFIG_405EP
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]172 #define mem_ecccf 0x94 /* ECC configuration */
173 #define mem_eccerr 0x98 /* ECC error status */
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]174#endif
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]175
stroeseb0ca12d2003-12-09 14:59:11 +0000[diff] [blame]176#ifndef CONFIG_405EP
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]177/******************************************************************************
178 * Decompression Controller
179 ******************************************************************************/
180#define DECOMP_DCR_BASE 0x14
181#define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */
182#define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */
183 /* values for kiar register - indirect addressing of these regs */
184 #define kitor0 0x00 /* index table origin register 0 */
185 #define kitor1 0x01 /* index table origin register 1 */
186 #define kitor2 0x02 /* index table origin register 2 */
187 #define kitor3 0x03 /* index table origin register 3 */
188 #define kaddr0 0x04 /* address decode definition regsiter 0 */
189 #define kaddr1 0x05 /* address decode definition regsiter 1 */
190 #define kconf 0x40 /* decompression core config register */
191 #define kid 0x41 /* decompression core ID register */
192 #define kver 0x42 /* decompression core version # reg */
193 #define kpear 0x50 /* bus error addr reg (PLB addr) */
194 #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/
195 #define kesr0 0x52 /* bus error status reg 0 (R/clear) */
196 #define kesr0s 0x53 /* bus error status reg 0 (set) */
197 /* There are 0x400 of the following registers, from krom0 to krom3ff*/
198 /* Only the first one is given here. */
199 #define krom0 0x400 /* SRAM/ROM read/write */
stroeseb0ca12d2003-12-09 14:59:11 +0000[diff] [blame]200#endif
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]201
202/******************************************************************************
203 * Power Management
204 ******************************************************************************/
205#define POWERMAN_DCR_BASE 0xb8
206#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */
207#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */
208#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */
209
210/******************************************************************************
211 * Extrnal Bus Controller
212 ******************************************************************************/
213#define EBC_DCR_BASE 0x12
214#define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */
215#define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */
216 /* values for ebccfga register - indirect addressing of these regs */
217 #define pb0cr 0x00 /* periph bank 0 config reg */
218 #define pb1cr 0x01 /* periph bank 1 config reg */
219 #define pb2cr 0x02 /* periph bank 2 config reg */
220 #define pb3cr 0x03 /* periph bank 3 config reg */
221 #define pb4cr 0x04 /* periph bank 4 config reg */
stroeseb0ca12d2003-12-09 14:59:11 +0000[diff] [blame]222#ifndef CONFIG_405EP
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]223 #define pb5cr 0x05 /* periph bank 5 config reg */
224 #define pb6cr 0x06 /* periph bank 6 config reg */
225 #define pb7cr 0x07 /* periph bank 7 config reg */
stroeseb0ca12d2003-12-09 14:59:11 +0000[diff] [blame]226#endif
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]227 #define pb0ap 0x10 /* periph bank 0 access parameters */
228 #define pb1ap 0x11 /* periph bank 1 access parameters */
229 #define pb2ap 0x12 /* periph bank 2 access parameters */
230 #define pb3ap 0x13 /* periph bank 3 access parameters */
231 #define pb4ap 0x14 /* periph bank 4 access parameters */
stroeseb0ca12d2003-12-09 14:59:11 +0000[diff] [blame]232#ifndef CONFIG_405EP
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]233 #define pb5ap 0x15 /* periph bank 5 access parameters */
234 #define pb6ap 0x16 /* periph bank 6 access parameters */
235 #define pb7ap 0x17 /* periph bank 7 access parameters */
stroeseb0ca12d2003-12-09 14:59:11 +0000[diff] [blame]236#endif
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]237 #define pbear 0x20 /* periph bus error addr reg */
238 #define pbesr0 0x21 /* periph bus error status reg 0 */
239 #define pbesr1 0x22 /* periph bus error status reg 1 */
240 #define epcr 0x23 /* external periph control reg */
241
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]242#ifdef CONFIG_405EP
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]243/******************************************************************************
244 * Control
245 ******************************************************************************/
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]246#define CNTRL_DCR_BASE 0x0f0
247#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */
248#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */
249#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */
250#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */
251#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */
252#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */
253
254#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
255#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
256#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
257#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/
258#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
259#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
260#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
261#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
262#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
263#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
264
265/* Bit definitions */
266#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */
267#define PLLMR0_CPU_DIV_BYPASS 0x00000000
268#define PLLMR0_CPU_DIV_2 0x00100000
269#define PLLMR0_CPU_DIV_3 0x00200000
270#define PLLMR0_CPU_DIV_4 0x00300000
271
272#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */
273#define PLLMR0_CPU_PLB_DIV_1 0x00000000
274#define PLLMR0_CPU_PLB_DIV_2 0x00010000
275#define PLLMR0_CPU_PLB_DIV_3 0x00020000
276#define PLLMR0_CPU_PLB_DIV_4 0x00030000
277
278#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */
279#define PLLMR0_OPB_PLB_DIV_1 0x00000000
280#define PLLMR0_OPB_PLB_DIV_2 0x00001000
281#define PLLMR0_OPB_PLB_DIV_3 0x00002000
282#define PLLMR0_OPB_PLB_DIV_4 0x00003000
283
284#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
285#define PLLMR0_EXB_PLB_DIV_2 0x00000000
286#define PLLMR0_EXB_PLB_DIV_3 0x00000100
287#define PLLMR0_EXB_PLB_DIV_4 0x00000200
288#define PLLMR0_EXB_PLB_DIV_5 0x00000300
289
290#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
291#define PLLMR0_MAL_PLB_DIV_1 0x00000000
292#define PLLMR0_MAL_PLB_DIV_2 0x00000010
293#define PLLMR0_MAL_PLB_DIV_3 0x00000020
294#define PLLMR0_MAL_PLB_DIV_4 0x00000030
295
296#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */
297#define PLLMR0_PCI_PLB_DIV_1 0x00000000
298#define PLLMR0_PCI_PLB_DIV_2 0x00000001
299#define PLLMR0_PCI_PLB_DIV_3 0x00000002
300#define PLLMR0_PCI_PLB_DIV_4 0x00000003
301
302#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */
303#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */
304#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
305#define PLLMR1_FBMUL_DIV_16 0x00000000
306#define PLLMR1_FBMUL_DIV_1 0x00100000
307#define PLLMR1_FBMUL_DIV_2 0x00200000
308#define PLLMR1_FBMUL_DIV_3 0x00300000
309#define PLLMR1_FBMUL_DIV_4 0x00400000
310#define PLLMR1_FBMUL_DIV_5 0x00500000
311#define PLLMR1_FBMUL_DIV_6 0x00600000
312#define PLLMR1_FBMUL_DIV_7 0x00700000
313#define PLLMR1_FBMUL_DIV_8 0x00800000
314#define PLLMR1_FBMUL_DIV_9 0x00900000
315#define PLLMR1_FBMUL_DIV_10 0x00A00000
316#define PLLMR1_FBMUL_DIV_11 0x00B00000
317#define PLLMR1_FBMUL_DIV_12 0x00C00000
318#define PLLMR1_FBMUL_DIV_13 0x00D00000
319#define PLLMR1_FBMUL_DIV_14 0x00E00000
320#define PLLMR1_FBMUL_DIV_15 0x00F00000
321
322#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
323#define PLLMR1_FWDVA_DIV_8 0x00000000
324#define PLLMR1_FWDVA_DIV_7 0x00010000
325#define PLLMR1_FWDVA_DIV_6 0x00020000
326#define PLLMR1_FWDVA_DIV_5 0x00030000
327#define PLLMR1_FWDVA_DIV_4 0x00040000
328#define PLLMR1_FWDVA_DIV_3 0x00050000
329#define PLLMR1_FWDVA_DIV_2 0x00060000
330#define PLLMR1_FWDVA_DIV_1 0x00070000
331#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
332#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
333
334/* Defines for CPC0_EPRCSR register */
335#define CPC0_EPRCSR_E0NFE 0x80000000
336#define CPC0_EPRCSR_E1NFE 0x40000000
337#define CPC0_EPRCSR_E1RPP 0x00000080
338#define CPC0_EPRCSR_E0RPP 0x00000040
339#define CPC0_EPRCSR_E1ERP 0x00000020
340#define CPC0_EPRCSR_E0ERP 0x00000010
341#define CPC0_EPRCSR_E1PCI 0x00000002
342#define CPC0_EPRCSR_E0PCI 0x00000001
343
344/* Defines for CPC0_PCI Register */
345#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */
346#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */
347#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/
348
349/* Defines for CPC0_BOOR Register */
350#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
351
352/* Defines for CPC0_PLLMR1 Register fields */
353#define PLL_ACTIVE 0x80000000
354#define CPC0_PLLMR1_SSCS 0x80000000
355#define PLL_RESET 0x40000000
356#define CPC0_PLLMR1_PLLR 0x40000000
357 /* Feedback multiplier */
358#define PLL_FBKDIV 0x00F00000
359#define CPC0_PLLMR1_FBDV 0x00F00000
360#define PLL_FBKDIV_16 0x00000000
361#define PLL_FBKDIV_1 0x00100000
362#define PLL_FBKDIV_2 0x00200000
363#define PLL_FBKDIV_3 0x00300000
364#define PLL_FBKDIV_4 0x00400000
365#define PLL_FBKDIV_5 0x00500000
366#define PLL_FBKDIV_6 0x00600000
367#define PLL_FBKDIV_7 0x00700000
368#define PLL_FBKDIV_8 0x00800000
369#define PLL_FBKDIV_9 0x00900000
370#define PLL_FBKDIV_10 0x00A00000
371#define PLL_FBKDIV_11 0x00B00000
372#define PLL_FBKDIV_12 0x00C00000
373#define PLL_FBKDIV_13 0x00D00000
374#define PLL_FBKDIV_14 0x00E00000
375#define PLL_FBKDIV_15 0x00F00000
376 /* Forward A divisor */
377#define PLL_FWDDIVA 0x00070000
378#define CPC0_PLLMR1_FWDVA 0x00070000
379#define PLL_FWDDIVA_8 0x00000000
380#define PLL_FWDDIVA_7 0x00010000
381#define PLL_FWDDIVA_6 0x00020000
382#define PLL_FWDDIVA_5 0x00030000
383#define PLL_FWDDIVA_4 0x00040000
384#define PLL_FWDDIVA_3 0x00050000
385#define PLL_FWDDIVA_2 0x00060000
386#define PLL_FWDDIVA_1 0x00070000
387 /* Forward B divisor */
388#define PLL_FWDDIVB 0x00007000
389#define CPC0_PLLMR1_FWDVB 0x00007000
390#define PLL_FWDDIVB_8 0x00000000
391#define PLL_FWDDIVB_7 0x00001000
392#define PLL_FWDDIVB_6 0x00002000
393#define PLL_FWDDIVB_5 0x00003000
394#define PLL_FWDDIVB_4 0x00004000
395#define PLL_FWDDIVB_3 0x00005000
396#define PLL_FWDDIVB_2 0x00006000
397#define PLL_FWDDIVB_1 0x00007000
398 /* PLL tune bits */
399#define PLL_TUNE_MASK 0x000003FF
400#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
401#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
402#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
403#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
404#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
405#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
406#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
407
408/* Defines for CPC0_PLLMR0 Register fields */
409 /* CPU divisor */
410#define PLL_CPUDIV 0x00300000
411#define CPC0_PLLMR0_CCDV 0x00300000
412#define PLL_CPUDIV_1 0x00000000
413#define PLL_CPUDIV_2 0x00100000
414#define PLL_CPUDIV_3 0x00200000
415#define PLL_CPUDIV_4 0x00300000
416 /* PLB divisor */
417#define PLL_PLBDIV 0x00030000
418#define CPC0_PLLMR0_CBDV 0x00030000
419#define PLL_PLBDIV_1 0x00000000
420#define PLL_PLBDIV_2 0x00010000
421#define PLL_PLBDIV_3 0x00020000
422#define PLL_PLBDIV_4 0x00030000
423 /* OPB divisor */
424#define PLL_OPBDIV 0x00003000
425#define CPC0_PLLMR0_OPDV 0x00003000
426#define PLL_OPBDIV_1 0x00000000
427#define PLL_OPBDIV_2 0x00001000
428#define PLL_OPBDIV_3 0x00002000
429#define PLL_OPBDIV_4 0x00003000
430 /* EBC divisor */
431#define PLL_EXTBUSDIV 0x00000300
432#define CPC0_PLLMR0_EPDV 0x00000300
433#define PLL_EXTBUSDIV_2 0x00000000
434#define PLL_EXTBUSDIV_3 0x00000100
435#define PLL_EXTBUSDIV_4 0x00000200
436#define PLL_EXTBUSDIV_5 0x00000300
437 /* MAL divisor */
438#define PLL_MALDIV 0x00000030
439#define CPC0_PLLMR0_MPDV 0x00000030
440#define PLL_MALDIV_1 0x00000000
441#define PLL_MALDIV_2 0x00000010
442#define PLL_MALDIV_3 0x00000020
443#define PLL_MALDIV_4 0x00000030
444 /* PCI divisor */
445#define PLL_PCIDIV 0x00000003
446#define CPC0_PLLMR0_PPFD 0x00000003
447#define PLL_PCIDIV_1 0x00000000
448#define PLL_PCIDIV_2 0x00000001
449#define PLL_PCIDIV_3 0x00000002
450#define PLL_PCIDIV_4 0x00000003
451
452/*
453 *-------------------------------------------------------------------------------
454 * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
455 * assuming a 33.3MHz input clock to the 405EP.
456 *-------------------------------------------------------------------------------
457 */
458#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]459 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
460 PLL_MALDIV_1 | PLL_PCIDIV_4)
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]461#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]462 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
463 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]464
465#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]466 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
467 PLL_MALDIV_1 | PLL_PCIDIV_4)
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]468#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]469 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
470 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]471#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]472 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
473 PLL_MALDIV_1 | PLL_PCIDIV_4)
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]474#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]475 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
476 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]477#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]478 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
479 PLL_MALDIV_1 | PLL_PCIDIV_4)
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]480#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]481 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
482 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]483
484/*
485 * PLL Voltage Controlled Oscillator (VCO) definitions
486 * Maximum and minimum values (in MHz) for correct PLL operation.
487 */
488#define VCO_MIN 500
489#define VCO_MAX 1000
490#else /* #ifdef CONFIG_405EP */
491/******************************************************************************
492 * Control
493 ******************************************************************************/
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]494#define CNTRL_DCR_BASE 0x0b0
495#define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */
496#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */
497#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */
498#define reset (CNTRL_DCR_BASE+0x3) /* reset register */
499#define strap (CNTRL_DCR_BASE+0x4) /* strap register */
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]500
501#define ecr (0xaa) /* edge conditioner register (405gpr) */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]502
503/* Bit definitions */
504#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
505#define PLLMR_FWD_DIV_BYPASS 0xE0000000
506#define PLLMR_FWD_DIV_3 0xA0000000
507#define PLLMR_FWD_DIV_4 0x80000000
508#define PLLMR_FWD_DIV_6 0x40000000
509
510#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
511#define PLLMR_FB_DIV_1 0x02000000
512#define PLLMR_FB_DIV_2 0x04000000
513#define PLLMR_FB_DIV_3 0x06000000
514#define PLLMR_FB_DIV_4 0x08000000
515
516#define PLLMR_TUNING_MASK 0x01F80000
517
518#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
519#define PLLMR_CPU_PLB_DIV_1 0x00000000
520#define PLLMR_CPU_PLB_DIV_2 0x00020000
521#define PLLMR_CPU_PLB_DIV_3 0x00040000
522#define PLLMR_CPU_PLB_DIV_4 0x00060000
523
524#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
525#define PLLMR_OPB_PLB_DIV_1 0x00000000
526#define PLLMR_OPB_PLB_DIV_2 0x00008000
527#define PLLMR_OPB_PLB_DIV_3 0x00010000
528#define PLLMR_OPB_PLB_DIV_4 0x00018000
529
530#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
531#define PLLMR_PCI_PLB_DIV_1 0x00000000
532#define PLLMR_PCI_PLB_DIV_2 0x00002000
533#define PLLMR_PCI_PLB_DIV_3 0x00004000
534#define PLLMR_PCI_PLB_DIV_4 0x00006000
535
536#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
537#define PLLMR_EXB_PLB_DIV_2 0x00000000
538#define PLLMR_EXB_PLB_DIV_3 0x00000800
539#define PLLMR_EXB_PLB_DIV_4 0x00001000
540#define PLLMR_EXB_PLB_DIV_5 0x00001800
541
542/* definitions for PPC405GPr (new mode strapping) */
543#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
544
545#define PSR_PLL_FWD_MASK 0xC0000000
546#define PSR_PLL_FDBACK_MASK 0x30000000
547#define PSR_PLL_TUNING_MASK 0x0E000000
548#define PSR_PLB_CPU_MASK 0x01800000
549#define PSR_OPB_PLB_MASK 0x00600000
550#define PSR_PCI_PLB_MASK 0x00180000
551#define PSR_EB_PLB_MASK 0x00060000
552#define PSR_ROM_WIDTH_MASK 0x00018000
553#define PSR_ROM_LOC 0x00004000
554#define PSR_PCI_ASYNC_EN 0x00001000
555#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */
556#define PSR_PCI_ARBIT_EN 0x00000400
557#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
558
559/*
560 * PLL Voltage Controlled Oscillator (VCO) definitions
561 * Maximum and minimum values (in MHz) for correct PLL operation.
562 */
563#define VCO_MIN 400
564#define VCO_MAX 800
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]565#endif /* #ifdef CONFIG_405EP */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]566
567/******************************************************************************
568 * Memory Access Layer
569 ******************************************************************************/
570#define MAL_DCR_BASE 0x180
571#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
572#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
573#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
574#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
575#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
576#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
577#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
578#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
579#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
580#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
581#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
582#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
583#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
584#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
585#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
586#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
587
588/*-----------------------------------------------------------------------------
589| IIC Register Offsets
590'----------------------------------------------------------------------------*/
591#define IICMDBUF 0x00
592#define IICSDBUF 0x02
593#define IICLMADR 0x04
594#define IICHMADR 0x05
595#define IICCNTL 0x06
596#define IICMDCNTL 0x07
597#define IICSTS 0x08
598#define IICEXTSTS 0x09
599#define IICLSADR 0x0A
600#define IICHSADR 0x0B
601#define IICCLKDIV 0x0C
602#define IICINTRMSK 0x0D
603#define IICXFRCNT 0x0E
604#define IICXTCNTLSS 0x0F
605#define IICDIRECTCNTL 0x10
606
607/*-----------------------------------------------------------------------------
608| UART Register Offsets
609'----------------------------------------------------------------------------*/
610#define DATA_REG 0x00
611#define DL_LSB 0x00
612#define DL_MSB 0x01
613#define INT_ENABLE 0x01
614#define FIFO_CONTROL 0x02
615#define LINE_CONTROL 0x03
616#define MODEM_CONTROL 0x04
617#define LINE_STATUS 0x05
618#define MODEM_STATUS 0x06
619#define SCRATCH 0x07
620
621/******************************************************************************
622 * On Chip Memory
623 ******************************************************************************/
624#define OCM_DCR_BASE 0x018
625#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */
626#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */
627#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */
628#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */
629
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]630/******************************************************************************
631 * GPIO macro register defines
632 ******************************************************************************/
633#define GPIO_BASE 0xEF600700
634#define GPIO0_OR (GPIO_BASE+0x0)
635#define GPIO0_TCR (GPIO_BASE+0x4)
636#define GPIO0_OSRH (GPIO_BASE+0x8)
637#define GPIO0_OSRL (GPIO_BASE+0xC)
638#define GPIO0_TSRH (GPIO_BASE+0x10)
639#define GPIO0_TSRL (GPIO_BASE+0x14)
640#define GPIO0_ODR (GPIO_BASE+0x18)
641#define GPIO0_IR (GPIO_BASE+0x1C)
642#define GPIO0_RR1 (GPIO_BASE+0x20)
643#define GPIO0_RR2 (GPIO_BASE+0x24)
644#define GPIO0_ISR1H (GPIO_BASE+0x30)
645#define GPIO0_ISR1L (GPIO_BASE+0x34)
646#define GPIO0_ISR2H (GPIO_BASE+0x38)
647#define GPIO0_ISR2L (GPIO_BASE+0x3C)
648
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]649
650/*
651 * Macro for accessing the indirect EBC register
652 */
653#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
654#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
655
656
657#ifndef __ASSEMBLY__
658
659typedef struct
660{
661 unsigned long pllFwdDiv;
662 unsigned long pllFwdDivB;
663 unsigned long pllFbkDiv;
664 unsigned long pllPlbDiv;
665 unsigned long pllPciDiv;
666 unsigned long pllExtBusDiv;
667 unsigned long pllOpbDiv;
668 unsigned long freqVCOMhz; /* in MHz */
669 unsigned long freqProcessor;
670 unsigned long freqPLB;
671 unsigned long freqPCI;
672 unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
673 unsigned long pciClkSync; /* PCI clock is synchronous */
674} PPC405_SYS_INFO;
675
676#endif /* _ASMLANGUAGE */
677
678#define RESET_VECTOR 0xfffffffc
679#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
680 line aligned data. */
681
682#endif /* __PPC405_H__ */