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git01.mediatek.com / filogic / uboot / c0ac6b74a3c22ee06dc5b21d54534da45f6ddab5 / . / include / fsl_errata.h
blob: 9f070726acb21c8bfcf06f97994394b702de8ba1 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
York Sunb1954252013-09-16 12:49:31 -0700[diff] [blame]2/*
Shengzhou Liu7d8dfb82015-11-20 15:52:03 +0800[diff] [blame]3 * Copyright 2013 - 2015 Freescale Semiconductor, Inc.
York Sunb1954252013-09-16 12:49:31 -0700[diff] [blame]4 */
5
Shengzhou Liu7d8dfb82015-11-20 15:52:03 +0800[diff] [blame]6#ifndef _FSL_ERRATA_H
7#define _FSL_ERRATA_H
York Sunb1954252013-09-16 12:49:31 -0700[diff] [blame]8
Shengzhou Liu7d8dfb82015-11-20 15:52:03 +0800[diff] [blame]9#if defined(CONFIG_PPC)
Tom Rinidec7ea02024-05-20 13:35:03 -0600[diff] [blame]10#include <asm/ppc.h>
York Sunc4f047c2017-03-27 11:41:03 -0700[diff] [blame]11#elif defined(CONFIG_ARCH_LS1021A)
Shengzhou Liu7d8dfb82015-11-20 15:52:03 +0800[diff] [blame]12#include <asm/arch-ls102xa/immap_ls102xa.h>
13#elif defined(CONFIG_FSL_LAYERSCAPE)
14#include <asm/arch/soc.h>
15#endif
16
York Sunb1954252013-09-16 12:49:31 -0700[diff] [blame]17
18#ifdef CONFIG_SYS_FSL_ERRATUM_A006379
19static inline bool has_erratum_a006379(void)
20{
21 u32 svr = get_svr();
22 if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) ||
Shengzhou Liu64ca4b42014-01-06 13:23:21 +0800[diff] [blame]23 ((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) ||
Shengzhou Liu26ed2d02014-04-25 16:31:22 +0800[diff] [blame]24 ((SVR_SOC_VER(svr) == SVR_T4080) && SVR_MAJ(svr) <= 1) ||
Shengzhou Liu64ca4b42014-01-06 13:23:21 +0800[diff] [blame]25 ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) ||
26 ((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) ||
27 ((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) ||
28 ((SVR_SOC_VER(svr) == SVR_T2081) && SVR_MAJ(svr) <= 1))
York Sunb1954252013-09-16 12:49:31 -0700[diff] [blame]29 return true;
30
31 return false;
32}
33#endif
Zhao Qiang440914d2014-10-30 14:07:39 +0800[diff] [blame]34
35#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
36static inline bool has_erratum_a007186(void)
37{
38 u32 svr = get_svr();
39 u32 soc = SVR_SOC_VER(svr);
40
41 switch (soc) {
42 case SVR_T4240:
43 return IS_SVR_REV(svr, 2, 0);
44 case SVR_T4160:
45 return IS_SVR_REV(svr, 2, 0);
46 case SVR_B4860:
47 return IS_SVR_REV(svr, 2, 0);
48 case SVR_B4420:
49 return IS_SVR_REV(svr, 2, 0);
50 case SVR_T2081:
51 case SVR_T2080:
Shengzhou Liu24e37d92015-03-09 17:12:22 +0800[diff] [blame]52 return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
Zhao Qiang440914d2014-10-30 14:07:39 +0800[diff] [blame]53 }
54
55 return false;
56}
57#endif
Shengzhou Liu7d8dfb82015-11-20 15:52:03 +0800[diff] [blame]58
Shengzhou Liu5a46e432015-11-20 15:52:04 +0800[diff] [blame]59#ifdef CONFIG_SYS_FSL_ERRATUM_A008378
60static inline bool has_erratum_a008378(void)
61{
62 u32 svr = get_svr();
63 u32 soc = SVR_SOC_VER(svr);
64
65
66 switch (soc) {
York Sunc4f047c2017-03-27 11:41:03 -0700[diff] [blame]67#ifdef CONFIG_ARCH_LS1021A
Shengzhou Liu5a46e432015-11-20 15:52:04 +0800[diff] [blame]68 case SOC_VER_LS1020:
69 case SOC_VER_LS1021:
70 case SOC_VER_LS1022:
71 case SOC_VER_SLS1020:
72 return IS_SVR_REV(svr, 1, 0);
73#endif
74#ifdef CONFIG_PPC
75 case SVR_T1023:
76 case SVR_T1024:
77 return IS_SVR_REV(svr, 1, 0);
78 case SVR_T1020:
79 case SVR_T1022:
80 case SVR_T1040:
81 case SVR_T1042:
82 return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
83#endif
84 default:
85 return false;
86 }
87}
88#endif
89
Shengzhou Liu7d8dfb82015-11-20 15:52:03 +0800[diff] [blame]90#endif /* _FSL_ERRATA_H */