| wdenk | 5f49575 | 2004-02-26 23:46:20 +0000 | [diff] [blame] | 1 | /*********************************************************************** |
| 2 | * |
| 3 | * Copyright (C) 2004 by FS Forth-Systeme GmbH. |
| 4 | * All rights reserved. |
| 5 | * |
| 6 | * $Id: ns9750_bbus.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $ |
| 7 | * @Author: Markus Pietrek |
| 8 | * @Descr: Definitions for BBus usage |
| 9 | * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 10 |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of |
| 14 | * the License, or (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 24 | * MA 02111-1307 USA |
| 25 | * |
| 26 | * |
| 27 | ***********************************************************************/ |
| 28 | |
| 29 | #ifndef FS_NS9750_BBUS_H |
| 30 | #define FS_NS9750_BBUS_H |
| 31 | |
| 32 | #define NS9750_BBUS_MODULE_BASE (0x90600000) |
| 33 | |
| 34 | #define get_bbus_reg_addr(c) \ |
| 35 | ((volatile unsigned int *)(NS9750_BBUS_MODULE_BASE+(unsigned int) (c))) |
| 36 | |
| 37 | /* We have support for 50 GPIO pins */ |
| 38 | |
| 39 | #define get_gpio_cfg_reg_addr(pin) \ |
| 40 | get_bbus_reg_addr( NS9750_BBUS_GPIO_CFG_BASE + (((pin) >> 3) * 4) ) |
| 41 | |
| 42 | /* To Read/Modify/Write a pin configuration register, use it like |
| 43 | set_gpio_cfg_reg_val( 12, NS9750_GPIO_CFG_FUNC_GPIO|NS9750_GPIO_CFG_OUTPUT ); |
| 44 | They should be wrapped by cli()/sti() */ |
| 45 | #define set_gpio_cfg_reg_val(pin,cfg) \ |
| 46 | *get_gpio_cfg_reg_addr(pin)=(*get_gpio_cfg_reg_addr((pin)) & \ |
| 47 | ~NS9750_GPIO_CFG_MASK((pin))) |\ |
| 48 | NS9750_GPIO_CFG_VAL((pin),(cfg)); |
| 49 | |
| 50 | #define NS9750_GPIO_CFG_MASK(pin) (NS9750_GPIO_CFG_VAL(pin, \ |
| 51 | NS9750_GPIO_CFG_MA)) |
| 52 | #define NS9750_GPIO_CFG_VAL(pin,cfg) ((cfg) << (((pin) % 8) * 4)) |
| 53 | |
| 54 | #define NS9750_GPIO_CFG_MA (0x0F) |
| 55 | #define NS9750_GPIO_CFG_INPUT (0x00) |
| 56 | #define NS9750_GPIO_CFG_OUTPUT (0x08) |
| 57 | #define NS9750_GPIO_CFG_FUNC_GPIO (0x03) |
| 58 | #define NS9750_GPIO_CFG_FUNC_2 (0x02) |
| 59 | #define NS9750_GPIO_CFG_FUNC_1 (0x01) |
| 60 | #define NS9750_GPIO_CFG_FUNC_0 (0x00) |
| 61 | |
| 62 | /* the register addresses */ |
| 63 | |
| 64 | #define NS9750_BBUS_MASTER_RESET (0x00) |
| 65 | #define NS9750_BBUS_GPIO_CFG_BASE (0x10) |
| 66 | #define NS9750_BBUS_GPIO_CTRL_BASE (0x30) |
| 67 | #define NS9750_BBUS_GPIO_STAT_BASE (0x40) |
| 68 | #define NS9750_BBUS_MONITOR (0x50) |
| 69 | #define NS9750_BBUS_DMA_INT_STAT (0x60) |
| 70 | #define NS9750_BBUS_DMA_INT_ENABLE (0x64) |
| 71 | #define NS9750_BBUS_USB_CFG (0x70) |
| 72 | #define NS9750_BBUS_ENDIAN_CFG (0x80) |
| 73 | #define NS9750_BBUS_ARM_WAKE_UP (0x90) |
| 74 | |
| 75 | /* register bit fields */ |
| 76 | |
| 77 | #define NS9750_BBUS_MASTER_RESET_UTIL (0x00000100) |
| 78 | #define NS9750_BBUS_MASTER_RESET_I2C (0x00000080) |
| 79 | #define NS9750_BBUS_MASTER_RESET_1284 (0x00000040) |
| 80 | #define NS9750_BBUS_MASTER_RESET_SER4 (0x00000020) |
| 81 | #define NS9750_BBUS_MASTER_RESET_SER3 (0x00000010) |
| 82 | #define NS9750_BBUS_MASTER_RESET_SER2 (0x00000008) |
| 83 | #define NS9750_BBUS_MASTER_RESET_SER1 (0x00000004) |
| 84 | #define NS9750_BBUS_MASTER_RESET_USB (0x00000002) |
| 85 | #define NS9750_BBUS_MASTER_RESET_DMA (0x00000001) |
| 86 | |
| 87 | /* BS9750_BBUS_DMA_INT_BINT* are valid for *DMA_INT_STAT and *DMA_INT_ENABLE */ |
| 88 | |
| 89 | #define NS9750_BBUS_DMA_INT_BINT16 (0x00010000) |
| 90 | #define NS9750_BBUS_DMA_INT_BINT15 (0x00008000) |
| 91 | #define NS9750_BBUS_DMA_INT_BINT14 (0x00004000) |
| 92 | #define NS9750_BBUS_DMA_INT_BINT13 (0x00002000) |
| 93 | #define NS9750_BBUS_DMA_INT_BINT12 (0x00001000) |
| 94 | #define NS9750_BBUS_DMA_INT_BINT11 (0x00000800) |
| 95 | #define NS9750_BBUS_DMA_INT_BINT10 (0x00000400) |
| 96 | #define NS9750_BBUS_DMA_INT_BINT9 (0x00000200) |
| 97 | #define NS9750_BBUS_DMA_INT_BINT8 (0x00000100) |
| 98 | #define NS9750_BBUS_DMA_INT_BINT7 (0x00000080) |
| 99 | #define NS9750_BBUS_DMA_INT_BINT6 (0x00000040) |
| 100 | #define NS9750_BBUS_DMA_INT_BINT5 (0x00000020) |
| 101 | #define NS9750_BBUS_DMA_INT_BINT4 (0x00000010) |
| 102 | #define NS9750_BBUS_DMA_INT_BINT3 (0x00000008) |
| 103 | #define NS9750_BBUS_DMA_INT_BINT2 (0x00000004) |
| 104 | #define NS9750_BBUS_DMA_INT_BINT1 (0x00000002) |
| 105 | #define NS9750_BBUS_DMA_INT_BINT0 (0x00000001) |
| 106 | |
| 107 | #define NS9750_BBUS_USB_CFG_OUTEN (0x00000008) |
| 108 | #define NS9750_BBUS_USB_CFG_SPEED (0x00000004) |
| 109 | #define NS9750_BBUS_USB_CFG_CFG_MA (0x00000003) |
| 110 | #define NS9750_BBUS_USB_CFG_CFG_HOST_SOFT (0x00000003) |
| 111 | #define NS9750_BBUS_USB_CFG_CFG_DEVICE (0x00000002) |
| 112 | #define NS9750_BBUS_USB_CFG_CFG_HOST (0x00000001) |
| 113 | #define NS9750_BBUS_USB_CFG_CFG_DIS (0x00000000) |
| 114 | |
| 115 | #define NS9750_BBUS_ENDIAN_CFG_AHBM (0x00001000) |
| 116 | #define NS9750_BBUS_ENDIAN_CFG_I2C (0x00000080) |
| 117 | #define NS9750_BBUS_ENDIAN_CFG_IEEE1284 (0x00000040) |
| 118 | #define NS9750_BBUS_ENDIAN_CFG_SER4 (0x00000020) |
| 119 | #define NS9750_BBUS_ENDIAN_CFG_SER3 (0x00000010) |
| 120 | #define NS9750_BBUS_ENDIAN_CFG_SER2 (0x00000008) |
| 121 | #define NS9750_BBUS_ENDIAN_CFG_SER1 (0x00000004) |
| 122 | #define NS9750_BBUS_ENDIAN_CFG_USB (0x00000002) |
| 123 | #define NS9750_BBUS_ENDIAN_CFG_DMA (0x00000001) |
| 124 | |
| 125 | #endif /* FS_NS9750_BBUS_H */ |