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git01.mediatek.com / filogic / uboot / c0931d0ec7044edd983305a2b9fd2960bc3aba26 / . / include / configs / bct-brettl2.h
blob: 36637aef95e9d78cc6a01a6ef392af50ced5b103 [file] [log] [blame]
Peter Meerwald9e9f4a42010-09-20 14:08:57 -0400[diff] [blame]1/*
2 * U-boot - Configuration file for BF536 brettl2 board
3 */
4
5#ifndef __CONFIG_BCT_BRETTL2_H__
6#define __CONFIG_BCT_BRETTL2_H__
7
8#include <asm/config-pre.h>
9
10
11/*
12 * Processor Settings
13 */
Mike Frysinger5b0c1282010-12-23 14:58:37 -0500[diff] [blame]14#define CONFIG_BFIN_CPU bf536-0.3
15#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
Peter Meerwald9e9f4a42010-09-20 14:08:57 -0400[diff] [blame]16
17
18/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 16384000
Wolfgang Denk1136f692010-10-27 22:48:30 +0200[diff] [blame]25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
Peter Meerwald9e9f4a42010-09-20 14:08:57 -0400[diff] [blame]27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
Wolfgang Denk1136f692010-10-27 22:48:30 +0200[diff] [blame]29/* 1 = bypass PLL */
Peter Meerwald9e9f4a42010-09-20 14:08:57 -0400[diff] [blame]30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 24
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
39#define CONFIG_SCLK_DIV 3
Wolfgang Denk1136f692010-10-27 22:48:30 +0200[diff] [blame]40#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)
Peter Meerwald9e9f4a42010-09-20 14:08:57 -0400[diff] [blame]41
42
43/*
44 * Memory Settings
45 */
46#define CONFIG_MEM_ADD_WDTH 9
47#define CONFIG_MEM_SIZE 32
48
49
50/*
51 * SDRAM Settings
52 */
53#define CONFIG_EBIU_SDRRC_VAL 0x07f6
54#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
55
56#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
57#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
58#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
59
60#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
61#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
62
63
64/*
65 * Network Settings
66 */
67#ifndef __ADSPBF534__
68#define ADI_CMDS_NETWORK 1
69#define CONFIG_BFIN_MAC 1
70#define CONFIG_NETCONSOLE 1
Peter Meerwald9e9f4a42010-09-20 14:08:57 -0400[diff] [blame]71#define CONFIG_HOSTNAME brettl2
72#define CONFIG_IPADDR 192.168.233.224
73#define CONFIG_GATEWAYIP 192.168.233.1
74#define CONFIG_SERVERIP 192.168.233.53
Joe Hershberger257ff782011-10-13 13:03:47 +0000[diff] [blame]75#define CONFIG_ROOTPATH "/romfs/brettl2"
Peter Meerwald9e9f4a42010-09-20 14:08:57 -0400[diff] [blame]76#endif
77
78
79/*
80 * Flash Settings
81 */
82#define CONFIG_FLASH_CFI_DRIVER
83#define CONFIG_SYS_FLASH_CFI
84#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
85#define CONFIG_SYS_FLASH_PROTECTION
86#define CONFIG_SYS_FLASH_BASE 0x20000000
87#define CONFIG_SYS_MAX_FLASH_BANKS 1
88#define CONFIG_SYS_MAX_FLASH_SECT 135
89
90
91/*
92 * Env Storage Settings
93 */
94#define CONFIG_ENV_IS_IN_FLASH 1
95#define CONFIG_ENV_OFFSET 0x4000
96#define CONFIG_ENV_SIZE 0x2000
Sonic Zhang61064dc2015-01-16 12:52:59 +0800[diff] [blame]97#define CONFIG_ENV_SECT_SIZE 0x12000
Peter Meerwald9e9f4a42010-09-20 14:08:57 -0400[diff] [blame]98
99#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
100#define ENV_IS_EMBEDDED
101#else
102#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
103#endif
104
105#ifdef ENV_IS_EMBEDDED
106/* WARNING - the following is hand-optimized to fit within
107 * the sector before the environment sector. If it throws
108 * an error during compilation remove an object here to get
109 * it linked after the configuration sector.
110 */
111# define LDS_BOARD_TEXT \
Masahiro Yamada30a198b2013-11-11 14:36:00 +0900[diff] [blame]112 arch/blackfin/lib/built-in.o (.text*); \
113 arch/blackfin/cpu/built-in.o (.text*); \
Wolfgang Denk1136f692010-10-27 22:48:30 +0200[diff] [blame]114 . = DEFINED(env_offset) ? env_offset : .; \
Mike Frysingera0d60412010-11-19 19:28:56 -0500[diff] [blame]115 common/env_embedded.o (.text*);
Peter Meerwald9e9f4a42010-09-20 14:08:57 -0400[diff] [blame]116#endif
117
118
119/*
120 * I2C Settings
121 */
Scott Jiang80d27fa2014-11-13 15:30:55 +0800[diff] [blame]122#define CONFIG_SYS_I2C
Scott Jiang655761e2014-11-13 15:30:53 +0800[diff] [blame]123#define CONFIG_SYS_I2C_ADI
Peter Meerwald9e9f4a42010-09-20 14:08:57 -0400[diff] [blame]124
125
126/*
127 * Misc Settings
128 */
129#define CONFIG_BOOTDELAY 1
130#define CONFIG_LOADADDR 0x800000
131#define CONFIG_MISC_INIT_R
132#define CONFIG_UART_CONSOLE 0
133#define CONFIG_BAUDRATE 115200
134#define CONFIG_MTD_DEVICE
135#define CONFIG_MTD_PARTITIONS
136#define CONFIG_SYS_HUSH_PARSER
Peter Meerwald9e9f4a42010-09-20 14:08:57 -0400[diff] [blame]137
138/*
139 * Pull in common ADI header for remaining command/environment setup
140 */
141#include <configs/bfin_adi_common.h>
142
143/* disable unnecessary features */
144#undef CONFIG_BOOTM_RTEMS
145#undef CONFIG_BZIP2
146#undef CONFIG_KALLSYMS
147
148#endif