| Mugunthan V N | bd2fb22 | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_TARGET_AM43XX_EVM=y | ||||
| Thomas Chou | 3a077cd | 2015-11-11 21:39:33 +0800 | [diff] [blame] | 3 | CONFIG_DM_SERIAL=y |
| Simon Glass | c08ebf6 | 2016-02-22 22:55:40 -0700 | [diff] [blame^] | 4 | CONFIG_DM_SPI=y |
| 5 | CONFIG_DM_SPI_FLASH=y | ||||
| Thomas Chou | 3a077cd | 2015-11-11 21:39:33 +0800 | [diff] [blame] | 6 | CONFIG_DM_GPIO=y |
| 7 | CONFIG_SPL_STACK_R_ADDR=0x82000000 | ||||
| Mugunthan V N | bd2fb22 | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 8 | CONFIG_DEFAULT_DEVICE_TREE="am437x-sk-evm" |
| 9 | CONFIG_SPL=y | ||||
| 10 | CONFIG_SPL_STACK_R=y | ||||
| Mugunthan V N | bd2fb22 | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 11 | CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1" |
| 12 | # CONFIG_CMD_IMLS is not set | ||||
| 13 | # CONFIG_CMD_FLASH is not set | ||||
| Thomas Chou | 3a077cd | 2015-11-11 21:39:33 +0800 | [diff] [blame] | 14 | CONFIG_CMD_GPIO=y |
| Mugunthan V N | bd2fb22 | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 15 | # CONFIG_CMD_SETEXPR is not set |
| 16 | CONFIG_OF_CONTROL=y | ||||
| Mugunthan V N | bd2fb22 | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 17 | CONFIG_DM=y |
| Mugunthan V N | bd2fb22 | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 18 | CONFIG_DM_MMC=y |
| Thomas Chou | 3a077cd | 2015-11-11 21:39:33 +0800 | [diff] [blame] | 19 | CONFIG_SPI_FLASH=y |
| Simon Glass | c08ebf6 | 2016-02-22 22:55:40 -0700 | [diff] [blame^] | 20 | CONFIG_SPI_FLASH_BAR=y |
| Bin Meng | 27f5b19 | 2015-11-25 05:34:54 -0800 | [diff] [blame] | 21 | CONFIG_SPI_FLASH_MACRONIX=y |
| Thomas Chou | a6cec01 | 2015-11-19 21:48:14 +0800 | [diff] [blame] | 22 | CONFIG_SYS_NS16550=y |
| Bin Meng | 72a049d | 2015-11-25 05:34:53 -0800 | [diff] [blame] | 23 | CONFIG_TI_QSPI=y |
| Mugunthan V N | 6c97b6d | 2015-12-24 16:08:10 +0530 | [diff] [blame] | 24 | CONFIG_TIMER=y |
| 25 | CONFIG_OMAP_TIMER=y | ||||
| Mugunthan V N | fe90ed9 | 2016-02-15 15:31:42 +0530 | [diff] [blame] | 26 | CONFIG_DMA=y |