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git01.mediatek.com / filogic / uboot / c0890d2e0e2b8e7717428d4b8dd3e7f1d03eb0ac / . / arch / arm / dts / zynqmp-sc-vpk180-revB.dtso
blob: e70eb4dc94784dbfe08f296e8b333065fe5840f3 [file] [log] [blame]
Michal Simekeaa6f3d2023-09-27 11:53:34 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx ZynqMP VPK180 revA
4 *
5 * (C) Copyright 2021 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
7 *
8 * Michal Simek <michal.simek@amd.com>
9 */
10
11#include <dt-bindings/gpio/gpio.h>
12
13/dts-v1/;
14/plugin/;
15
16
17&{/} {
18 compatible = "xlnx,zynqmp-sc-vpk180-revB", "xlnx,zynqmp-vpk180-revB",
19 "xlnx,zynqmp-vpk180", "xlnx,zynqmp";
20
21 vc7_xin: vc7-xin {
22 compatible = "fixed-clock";
23 #clock-cells = <0x0>;
24 clock-frequency = <50000000>;
25 };
26};
27
28&i2c0 {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 tca6416_u233: gpio@20 { /* u233 */
33 compatible = "ti,tca6416";
34 reg = <0x20>;
35 gpio-controller; /* interrupt not connected */
36 #gpio-cells = <2>;
37 gpio-line-names = "QSFPDD1_MODSELL", "QSFPDD2_MODSELL", "QSFPDD3_MODSELL", "QSFPDD4_MODSELL", /* 0 - 3 */
38 "PMBUS2_INA226_ALERT", "QSFPDD5_MODSELL", "QSFPDD6_MODSELL", "", /* 4 - 7 */
39 "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "UTIL_3V3_VRHOT_B", /* 10 - 13 */
40 "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
41 };
42
43 i2c-mux@74 { /* u33 */
44 compatible = "nxp,pca9548";
45 #address-cells = <1>;
46 #size-cells = <0>;
47 reg = <0x74>;
48 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
49 pmbus_i2c: i2c@0 {
50 #address-cells = <1>;
51 #size-cells = <0>;
52 reg = <0>;
53 /* On connector J325 */
54 ir38060_41: regulator@41 { /* IR38060 - u259 */
55 compatible = "infineon,ir38060", "infineon,ir38064";
56 reg = <0x41>; /* i2c addr 0x11 */
57 };
58 ir35221_45: pmic@45 { /* IR35221 - u291 */
59 compatible = "infineon,ir35221";
60 reg = <0x45>; /* i2c addr - 0x15 */
61 };
62 ir35221_46: pmic@46 { /* IR35221 - u152 */
63 compatible = "infineon,ir35221";
64 reg = <0x46>; /* i2c addr - 0x16 */
65 };
66 irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
67 compatible = "infineon,irps5401";
68 reg = <0x47>; /* i2c addr 0x17 */
69 };
70 irps5401_48: pmic@48 { /* IRPS5401 - u295 */
71 compatible = "infineon,irps5401";
72 reg = <0x48>; /* i2c addr 0x18 */
73 };
74 ir38164_49: regulator@49 { /* IR38164 - u189 */
75 compatible = "infineon,ir38164";
76 reg = <0x49>; /* i2c addr 0x19 */
77 };
78 irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
79 compatible = "infineon,irps5401";
80 reg = <0x4c>; /* i2c addr 0x1c */
81 };
82 irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
83 compatible = "infineon,irps5401";
84 reg = <0x4d>; /* i2c addr 0x1d */
85 };
86 ir38164_4e: regulator@4e { /* IR38164 - u185 */
87 compatible = "infineon,ir38164";
88 reg = <0x4e>; /* i2c addr 0x1e */
89 };
90 ir38164_4f: regulator@4f { /* IR38164 - u187 */
91 compatible = "infineon,ir38164";
92 reg = <0x4f>; /* i2c addr 0x1f */
93 };
94 };
95 pmbus1_ina226_i2c: i2c@1 {
96 #address-cells = <1>;
97 #size-cells = <0>;
98 reg = <1>;
99 /* FIXME check alerts coming to SC */
100 vccint: ina226@40 { /* u65 */
101 compatible = "ti,ina226";
102 reg = <0x40>;
103 shunt-resistor = <5000>; /* r440 */
104 };
105 vcc_soc: ina226@41 { /* u161 */
106 compatible = "ti,ina226";
107 reg = <0x41>;
108 shunt-resistor = <5000>; /* r2174 */
109 };
110 vcc_pmc: ina226@42 { /* u163 */
111 compatible = "ti,ina226";
112 reg = <0x42>;
113 shunt-resistor = <5000>; /* r1214 */
114 };
115 vcc_ram: ina226@43 { /* u5 */
116 compatible = "ti,ina226";
117 reg = <0x43>;
118 shunt-resistor = <5000>; /* r2108 */
119 };
120 vcc_pslp: ina226@44 { /* u165 */
121 compatible = "ti,ina226";
122 reg = <0x44>;
123 shunt-resistor = <5000>; /* r1830 */
124 };
125 vcc_psfp: ina226@45 { /* u164 */
126 compatible = "ti,ina226";
127 reg = <0x45>;
128 shunt-resistor = <5000>; /* r2086 */
129 };
130 };
131 i2c@2 { /* NC */ /* FIXME maybe remove */
132 #address-cells = <1>;
133 #size-cells = <0>;
134 reg = <2>;
135 };
136 pmbus2_ina226_i2c: i2c@3 {
137 #address-cells = <1>;
138 #size-cells = <0>;
139 reg = <3>;
140 /* FIXME check alerts coming to SC */
141 vccaux: ina226@40 { /* u166 */
142 compatible = "ti,ina226";
143 reg = <0x40>;
144 shunt-resistor = <2000>; /* r2109 */
145 };
146 vccaux_pmc: ina226@41 { /* u168 */
147 compatible = "ti,ina226";
148 reg = <0x41>;
149 shunt-resistor = <5000>; /* r1246 */
150 };
151 mgtavcc: ina226@42 { /* u265 */
152 compatible = "ti,ina226";
153 reg = <0x42>;
154 shunt-resistor = <5000>; /* r1829 */
155 };
156 vcc1v5: ina226@43 { /* u264 */
157 compatible = "ti,ina226";
158 reg = <0x43>;
159 shunt-resistor = <5000>; /* r1221 */
160 };
161 vcco_mio: ina226@45 { /* u172 */
162 compatible = "ti,ina226";
163 reg = <0x45>;
164 shunt-resistor = <5000>; /* r1219 */
165 };
166 mgtavtt: ina226@46 { /* u188 */
167 compatible = "ti,ina226";
168 reg = <0x46>;
169 shunt-resistor = <2000>; /* r1384 */
170 };
171 vcco_502: ina226@47 { /* u174 */
172 compatible = "ti,ina226";
173 reg = <0x47>;
174 shunt-resistor = <5000>; /* r1825 */
175 };
176 mgtvccaux: ina226@48 { /* u176 */
177 compatible = "ti,ina226";
178 reg = <0x48>;
179 shunt-resistor = <5000>; /* r1232 */
180 };
181 vcc1v1_lp4: ina226@49 { /* u186 */
182 compatible = "ti,ina226";
183 reg = <0x49>;
184 shunt-resistor = <2000>; /* r1367 */
185 };
186 vadj_fmc: ina226@4a { /* u184 */
187 compatible = "ti,ina226";
188 reg = <0x4a>;
189 shunt-resistor = <2000>; /* r1350 */
190 };
191 lpdmgtyavcc: ina226@4b { /* u177 */
192 compatible = "ti,ina226";
193 reg = <0x4b>;
194 shunt-resistor = <5000>; /* r2097 */
195 };
196 lpdmgtyavtt: ina226@4c { /* u260 */
197 compatible = "ti,ina226";
198 reg = <0x4c>;
199 shunt-resistor = <2000>; /* r1834 */
200 };
201 lpdmgtyvccaux: ina226@4d { /* u234 */
202 compatible = "ti,ina226";
203 reg = <0x4d>;
204 shunt-resistor = <5000>; /* r1679 */
205 };
206 };
207 /* 4 - 7 unused */
208 };
209};
210
211&i2c1 {
212 #address-cells = <1>;
213 #size-cells = <0>;
214
215 i2c-mux@74 { /* u35 */
216 compatible = "nxp,pca9548";
217 #address-cells = <1>;
218 #size-cells = <0>;
219 reg = <0x74>;
220 i2c-mux-idle-disconnect;
221 /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
222 i2c@0 {
223 #address-cells = <1>;
224 #size-cells = <0>;
225 reg = <0>;
226 };
227 fmcp1_i2c: i2c@1 {
228 #address-cells = <1>;
229 #size-cells = <0>;
230 reg = <1>;
231 /* connection to Samtec J51C */
232 /* expected eeprom 0x50 SE cards */
233 };
234 osfp_i2c: i2c@2 {
235 #address-cells = <1>;
236 #size-cells = <0>;
237 reg = <2>;
238 /* J362 connector */
239 };
240 i2c@3 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 reg = <3>;
244 /* alternative option DNP - u305 at 0x50 */
245 };
246 i2c@4 {
247 #address-cells = <1>;
248 #size-cells = <0>;
249 reg = <4>;
250 /* alternative option DNP - u303 at 0x50 */
251 };
252 i2c@5 {
253 #address-cells = <1>;
254 #size-cells = <0>;
255 reg = <5>;
256 /* alternative option DNP - u301 at 0x50 */
257 };
258 qsfpdd_i2c: i2c@6 {
259 #address-cells = <1>;
260 #size-cells = <0>;
261 reg = <6>;
262 /* J1/J2/J355/J354/J359/J358 connectors */
263 };
264 idt8a34001_i2c: i2c@7 {
265 #address-cells = <1>;
266 #size-cells = <0>;
267 reg = <7>;
268 /* Via J310 connector */
269 idt_8a34001: phc@5b { /* u219B */
270 compatible = "idt,8a34001";
271 reg = <0x5b>;
272 };
273 };
274 };
275 i2c-mux@75 { /* u322 */
276 compatible = "nxp,pca9548";
277 #address-cells = <1>;
278 #size-cells = <0>;
279 reg = <0x75>;
280 i2c-mux-idle-disconnect;
281 /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
282 sfpdd1_i2c: i2c@0 {
283 #address-cells = <1>;
284 #size-cells = <0>;
285 reg = <0>;
286 /* J350 sfp-dd at 0x50 */
287 };
288 sfpdd2_i2c: i2c@1 {
289 #address-cells = <1>;
290 #size-cells = <0>;
291 reg = <1>;
292 /* J352 sfp-dd at 0x50 */
293 };
294 sfpdd3_i2c: i2c@2 {
295 #address-cells = <1>;
296 #size-cells = <0>;
297 reg = <2>;
298 /* J385 sfp-dd at 0x50 */
299 };
300 sfpdd4_i2c: i2c@3 {
301 #address-cells = <1>;
302 #size-cells = <0>;
303 reg = <3>;
304 /* J387 sfp-dd at 0x50 */
305 };
306 rc21008a_gtclk1_i2c: i2c@4 {
307 #address-cells = <1>;
308 #size-cells = <0>;
309 reg = <4>;
310 vc7_1: clock-generator@9 {
311 compatible = "renesas,rc21008a";
312 clock-output-names = "rc21008a-0";
313 reg = <0x9>;
314 #clock-cells = <1>;
315 clocks = <&vc7_xin>;
316 clock-names = "xin";
317 };
318 /* u298 - rc21008a at 0x9 */
319 /* connector J370 */
320 };
321 rc21008a_gtclk2_i2c: i2c@5 {
322 #address-cells = <1>;
323 #size-cells = <0>;
324 reg = <5>;
325 vc7_2: clock-generator@9 {
326 compatible = "renesas,rc21008a";
327 clock-output-names = "rc21008a-1";
328 reg = <0x9>;
329 #clock-cells = <1>;
330 clocks = <&vc7_xin>;
331 clock-names = "xin";
332 };
333 /* u299 - rc21008a at 0x9 */
334 /* connector J371 */
335 };
336 };
337};