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git01.mediatek.com / filogic / uboot / c0890d2e0e2b8e7717428d4b8dd3e7f1d03eb0ac / . / arch / arm / dts / zynqmp-sc-vhk158-revA.dtso
blob: 2ce69374c15464a31c0232f03c402eda78bcb7e0 [file] [log] [blame]
Michal Simekeaa6f3d2023-09-27 11:53:34 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx ZynqMP VHK158 revA
4 *
5 * (C) Copyright 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
7 *
8 * Michal Simek <michal.simek@amd.com>
9 */
10
11#include <dt-bindings/gpio/gpio.h>
12
13/dts-v1/;
14/plugin/;
15
16&{/} {
17 compatible = "xlnx,zynqmp-sc-vhk158-revA", "xlnx,zynqmp-vhk158-revA",
18 "xlnx,zynqmp-vhk158", "xlnx,zynqmp";
19
20 vc7_xin: vc7-xin {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <50000000>;
24 };
25};
26
27&i2c0 {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 tca6416_u233: gpio@20 { /* u233 */
32 compatible = "ti,tca6416";
33 reg = <0x20>;
34 gpio-controller; /* interrupt not connected */
35 #gpio-cells = <2>;
36 gpio-line-names = "", "", "QSFPDD1_MODSELL", "QSFPDD2_MODSELL", /* 0 - 3 */
37 "PMBUS2_INA226_ALERT", "", "", "", /* 4 - 7 */
38 "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */
39 "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
40 };
41
42 i2c-mux@74 { /* u33 */
43 compatible = "nxp,pca9548";
44 #address-cells = <1>;
45 #size-cells = <0>;
46 reg = <0x74>;
47 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
48 pmbus_i2c: i2c@0 {
49 #address-cells = <1>;
50 #size-cells = <0>;
51 reg = <0>;
52 /* On connector J325 */
53 ir38064_41: regulator@41 { /* IR38064 - u294 */
54 compatible = "infineon,ir38064";
55 reg = <0x41>; /* i2c addr 0x11 */
56 };
57 irps5401_45: pmic5401@45 { /* IRPS5401 - u280 */
58 compatible = "infineon,irps5401";
59 reg = <0x45>; /* i2c addr 0x15 */
60 };
61 ir35221_46: pmic@46 { /* IR35221 - u152 */
62 compatible = "infineon,ir35221";
63 reg = <0x46>; /* i2c addr - 0x16 */
64 };
65 irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
66 compatible = "infineon,irps5401";
67 reg = <0x47>; /* i2c addr 0x17 */
68 };
69 irps5401_48: regulator@48 { /* IRPS5401 - u279 */
70 compatible = "infineon,irps5401";
71 reg = <0x48>; /* i2c addr 0x18 */
72 };
73 ir38164_49: regulator@49 { /* IR38164 - u295 */
74 compatible = "infineon,ir38164";
75 reg = <0x49>; /* i2c addr 0x19 */
76 };
77 ir38060_4a: regulator@4a { /* IR38060 - u259 */
78 compatible = "infineon,ir38164";
79 reg = <0x4a>; /* i2c addr 0x1a */
80 };
81 irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
82 compatible = "infineon,irps5401";
83 reg = <0x4c>; /* i2c addr 0x1c */
84 };
85 irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
86 compatible = "infineon,irps5401";
87 reg = <0x4d>; /* i2c addr 0x1d */
88 };
89 ir38060_4e: regulator@4e { /* IR38060 - u282 */
90 compatible = "infineon,ir38164";
91 reg = <0x4e>; /* i2c addr 0x1e */
92 };
93 };
94 pmbus1_ina226_i2c: i2c@1 {
95 #address-cells = <1>;
96 #size-cells = <0>;
97 reg = <1>;
98 /* FIXME check alerts coming to SC */
99 vccint: ina226@40 { /* u65 */
100 compatible = "ti,ina226";
101 reg = <0x40>;
102 shunt-resistor = <500>; /* R440 */
103 };
104 vcc_soc: ina226@41 { /* u161 */
105 compatible = "ti,ina226";
106 reg = <0x41>;
107 shunt-resistor = <500>; /* R1702 */
108 };
109 vcc_pmc: ina226@42 { /* u163 */
110 compatible = "ti,ina226";
111 reg = <0x42>;
112 shunt-resistor = <5000>; /* R382 */
113 };
114 vcc_ram: ina226@43 { /* u5 */
115 compatible = "ti,ina226";
116 reg = <0x43>;
117 shunt-resistor = <500>; /* R121 */
118 };
119 vcc_pslp: ina226@44 { /* u165 */
120 compatible = "ti,ina226";
121 reg = <0x44>;
122 shunt-resistor = <5000>; /* R1830 */
123 };
124 vcc_psfp: ina226@45 { /* u260 */
125 compatible = "ti,ina226";
126 reg = <0x45>;
127 shunt-resistor = <5000>; /* R1834 */
128 };
129 vcco_hbm: ina226@46 { /* u164 */
130 compatible = "ti,ina226";
131 reg = <0x46>;
132 shunt-resistor = <500>; /* R2056 */
133 };
134 vcc_hbm: ina226@47 { /* u307 */
135 compatible = "ti,ina226";
136 reg = <0x47>;
137 shunt-resistor = <500>; /* R2068 */
138 };
139 vccaux_hbm: ina226@48 { /* u308 */
140 compatible = "ti,ina226";
141 reg = <0x48>;
142 shunt-resistor = <5000>; /* R2019 */
143 };
144 };
145 i2c@2 { /* NC */ /* FIXME maybe remove */
146 #address-cells = <1>;
147 #size-cells = <0>;
148 reg = <2>;
149 };
150 pmbus2_ina226_i2c: i2c@3 {
151 #address-cells = <1>;
152 #size-cells = <0>;
153 reg = <3>;
154 /* FIXME check alerts coming to SC */
155 vccaux: ina226@40 { /* u166 */
156 compatible = "ti,ina226";
157 reg = <0x40>;
158 shunt-resistor = <5000>; /* R2060 */
159 };
160 vccaux_pmc: ina226@41 { /* u168 */
161 compatible = "ti,ina226";
162 reg = <0x41>;
163 shunt-resistor = <500>; /* R2000 */
164 };
165 mgtavcc: ina226@42 { /* u265 */
166 compatible = "ti,ina226";
167 reg = <0x42>;
168 shunt-resistor = <500>; /* R1829 */
169 };
170 vcc1v5: ina226@43 { /* u264 */
171 compatible = "ti,ina226";
172 reg = <0x43>;
173 shunt-resistor = <500>; /* R1221 */
174 };
175 vcco_mio: ina226@45 { /* u172 */
176 compatible = "ti,ina226";
177 reg = <0x45>;
178 shunt-resistor = <500>; /* R2015 */
179 };
180 mgtavtt: ina226@46 { /* u188 */
181 compatible = "ti,ina226";
182 reg = <0x46>;
183 shunt-resistor = <500>; /* R1384 */
184 };
185 vcco_502: ina226@47 { /* u174 */
186 compatible = "ti,ina226";
187 reg = <0x47>;
188 shunt-resistor = <500>; /* R1994 */
189 };
190 mgtvccaux: ina226@48 { /* u176 */
191 compatible = "ti,ina226";
192 reg = <0x48>;
193 shunt-resistor = <500>; /* R1232 */
194 };
195 vcc1v2_rdimm: ina226@49 { /* u306 */
196 compatible = "ti,ina226";
197 reg = <0x49>;
198 shunt-resistor = <500>; /* R2064 */
199 };
200 vadj_fmc: ina226@4a { /* u281 */
201 compatible = "ti,ina226";
202 reg = <0x4a>;
203 shunt-resistor = <5000>; /* R2031 */
204 };
205 lpdmgtyavcc: ina226@4b { /* u177 */
206 compatible = "ti,ina226";
207 reg = <0x4b>;
208 shunt-resistor = <500>; /* R2004 */
209 };
210 lpdmgtyavtt: ina226@4c { /* u309 */
211 compatible = "ti,ina226";
212 reg = <0x4c>;
213 shunt-resistor = <500>; /* R1229 */
214 };
215 lpdmgtyvccaux: ina226@4d { /* u234 */
216 compatible = "ti,ina226";
217 reg = <0x4d>;
218 shunt-resistor = <500>; /* R1679 */
219 };
220 };
221 i2c@4 { /* NC */
222 #address-cells = <1>;
223 #size-cells = <0>;
224 reg = <4>;
225 };
226 rc21008a_gtclk1: i2c@5 {
227 #address-cells = <1>;
228 #size-cells = <0>;
229 reg = <5>;
230 vc7_1: clock-generator@9 {
231 compatible = "renesas,rc21008a";
232 clock-output-names = "rc21008a-0";
233 reg = <0x9>;
234 #clock-cells = <1>;
235 clocks = <&vc7_xin>;
236 clock-names = "xin";
237 };
238 /* i2c@9 - U299 */
239 };
240 rc21008a_gtclk2: i2c@6 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 reg = <6>;
244 vc7_2: clock-generator@9 {
245 compatible = "renesas,rc21008a";
246 clock-output-names = "rc21008a-1";
247 reg = <0x9>;
248 #clock-cells = <1>;
249 clocks = <&vc7_xin>;
250 clock-names = "xin";
251 };
252 /* i2c@9 - U300 */
253 };
254 sync_8a34001: i2c@7 {
255 #address-cells = <1>;
256 #size-cells = <0>;
257 reg = <7>;
258 /* U219 - i2c address UNKNOWN */
259 };
260 };
261};
262
263&i2c1 {
264 #address-cells = <1>;
265 #size-cells = <0>;
266
267 i2c-mux@74 { /* u35 */
268 compatible = "nxp,pca9548";
269 #address-cells = <1>;
270 #size-cells = <0>;
271 reg = <0x74>;
272 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
273 ddr4_dimm0: i2c@0 { /* wired but NC */
274 #address-cells = <1>;
275 #size-cells = <0>;
276 reg = <0>;
277 };
278 fmcp1_i2c: i2c@1 {
279 #address-cells = <1>;
280 #size-cells = <0>;
281 reg = <1>;
282 /* FIXME connection to Samtec J51C */
283 /* expected eeprom 0x50 SE cards */
284 };
285 qsfp1_i2c: i2c@2 {
286 #address-cells = <1>;
287 #size-cells = <0>;
288 reg = <2>;
289 /* J350 connector */
290 };
291 qsfp2_i2c: i2c@3 {
292 #address-cells = <1>;
293 #size-cells = <0>;
294 reg = <3>;
295 /* J351 connector */
296 };
297 qsfp3_i2c: i2c@4 {
298 #address-cells = <1>;
299 #size-cells = <0>;
300 reg = <4>;
301 /* J352 connector */
302 };
303 qsfp4_i2c: i2c@5 {
304 #address-cells = <1>;
305 #size-cells = <0>;
306 reg = <5>;
307 /* J353 connector */
308 };
309 qsfpdd_i2c: i2c@6 {
310 #address-cells = <1>;
311 #size-cells = <0>;
312 reg = <6>;
313 /* J1/J2 connectors */
314 };
315 ddr4_dimm1: i2c@7 { /* wired but NC */
316 #address-cells = <1>;
317 #size-cells = <0>;
318 reg = <7>;
319 };
320 };
321};