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git01.mediatek.com / filogic / uboot / c07ac74db6ee9a27f3dbd246e49c54018661a746 / . / arch / arm / dts / k3-am654-r5-base-board-u-boot.dtsi
blob: 4516ab1437e73399de4bada4f90c08c89c7b8bc5 [file] [log] [blame]
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018-2021 Texas Instruments Incorporated - http://www.ti.com/
4 */
5
6#include <dt-bindings/pinctrl/k3.h>
7#include <dt-bindings/net/ti-dp83867.h>
8
9/ {
10 chosen {
11 stdout-path = "serial2:115200n8";
12 };
13
14 aliases {
15 serial2 = &main_uart0;
16 ethernet0 = &cpsw_port1;
17 usb0 = &usb0;
18 usb1 = &usb1;
19 spi0 = &ospi0;
20 spi1 = &ospi1;
21 };
22};
23
24&cbass_main{
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]25 bootph-pre-ram;
Tom Rinif8276452021-09-10 17:37:43 -0400[diff] [blame]26 main_navss: bus@30800000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]27 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]28 };
29};
30
31&cbass_mcu {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]32 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]33
Tom Rinif8276452021-09-10 17:37:43 -0400[diff] [blame]34 mcu_navss: bus@28380000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]35 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]36
37 ringacc@2b800000 {
38 reg = <0x0 0x2b800000 0x0 0x400000>,
39 <0x0 0x2b000000 0x0 0x400000>,
40 <0x0 0x28590000 0x0 0x100>,
41 <0x0 0x2a500000 0x0 0x40000>,
42 <0x0 0x28440000 0x0 0x40000>;
43 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]44 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]45 ti,dma-ring-reset-quirk;
46 };
47
48 dma-controller@285c0000 {
49 reg = <0x0 0x285c0000 0x0 0x100>,
50 <0x0 0x284c0000 0x0 0x4000>,
51 <0x0 0x2a800000 0x0 0x40000>,
52 <0x0 0x284a0000 0x0 0x4000>,
53 <0x0 0x2aa00000 0x0 0x40000>,
54 <0x0 0x28400000 0x0 0x2000>;
55 reg-names = "gcfg", "rchan", "rchanrt", "tchan",
56 "tchanrt", "rflow";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]57 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]58 };
59 };
60};
61
62&cbass_wakeup {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]63 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]64
65 chipid@43000014 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]66 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]67 };
68};
69
70&secure_proxy_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]71 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]72};
73
74&dmsc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]75 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]76 k3_sysreset: sysreset-controller {
77 compatible = "ti,sci-sysreset";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]78 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]79 };
80};
81
82&k3_pds {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]83 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]84};
85
86&k3_clks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]87 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]88};
89
90&k3_reset {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]91 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]92};
93
94&wkup_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]95 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]96
97 wkup_i2c0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]98 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]99 };
100};
101
102&main_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]103 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]104 usb0_pins_default: usb0_pins_default {
105 pinctrl-single,pins = <
106 AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
107 >;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]108 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]109 };
110};
111
112&main_uart0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]113 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]114};
115
116&main_pmx1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]117 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]118};
119
120&wkup_pmx0 {
121 mcu-fss0-ospi0-pins-default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]122 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]123 };
124};
125
126&main_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]127 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]128};
129
130&main_mmc0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]131 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]132};
133
134&main_mmc1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]135 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]136};
137
138&sdhci0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]139 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]140};
141
142&sdhci1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]143 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]144};
145
146&davinci_mdio {
147 phy0: ethernet-phy@0 {
148 reg = <0>;
149 /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
150 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
151 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
152 };
153};
154
155&mcu_cpsw {
156 reg = <0x0 0x46000000 0x0 0x200000>,
157 <0x0 0x40f00200 0x0 0x2>;
158 reg-names = "cpsw_nuss", "mac_efuse";
159 /delete-property/ ranges;
160
161 cpsw-phy-sel@40f04040 {
162 compatible = "ti,am654-cpsw-phy-sel";
163 reg= <0x0 0x40f04040 0x0 0x4>;
164 reg-names = "gmii-sel";
165 };
166};
167
168&wkup_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]169 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]170};
171
172&usb1 {
173 dr_mode = "peripheral";
174};
175
176&fss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]177 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]178};
179
180&ospi0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]181 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]182
183 flash@0{
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]184 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]185 };
186};
187
188&dwc3_0 {
189 status = "okay";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]190 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]191};
192
193&usb0_phy {
194 status = "okay";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]195 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]196};
197
198&usb0 {
199 pinctrl-names = "default";
200 pinctrl-0 = <&usb0_pins_default>;
Aswath Govindraju57c687b2022-05-18 16:49:12 +0530[diff] [blame]201 dr_mode = "peripheral";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]202 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]203};
204
205&scm_conf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]206 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]207};