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Jagan Teki1d150b42018-12-22 21:32:49 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
Jagan Teki1d150b42018-12-22 21:32:49 +05307#include <clk-uclass.h>
8#include <dm.h>
9#include <errno.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Andre Przywara030bab82019-01-29 15:54:08 +000011#include <reset.h>
Jagan Teki1d150b42018-12-22 21:32:49 +053012#include <asm/io.h>
Samuel Holland12e3faa2021-09-12 11:48:43 -050013#include <clk/sunxi.h>
Samuel Holland86b561c2022-05-09 00:29:37 -050014#include <dm/device-internal.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060015#include <linux/bitops.h>
Jagan Teki1d150b42018-12-22 21:32:49 +053016#include <linux/log2.h>
17
Samuel Holland86b561c2022-05-09 00:29:37 -050018extern U_BOOT_DRIVER(sunxi_reset);
19
Samuel Holland90315322022-05-09 00:29:35 -050020static const struct ccu_clk_gate *plat_to_gate(struct ccu_plat *plat,
Jagan Teki1d150b42018-12-22 21:32:49 +053021 unsigned long id)
22{
Samuel Holland90315322022-05-09 00:29:35 -050023 if (id >= plat->desc->num_gates)
Samuel Hollanda4969072022-05-09 00:29:32 -050024 return NULL;
25
Samuel Holland90315322022-05-09 00:29:35 -050026 return &plat->desc->gates[id];
Jagan Teki1d150b42018-12-22 21:32:49 +053027}
28
29static int sunxi_set_gate(struct clk *clk, bool on)
30{
Samuel Holland90315322022-05-09 00:29:35 -050031 struct ccu_plat *plat = dev_get_plat(clk->dev);
32 const struct ccu_clk_gate *gate = plat_to_gate(plat, clk->id);
Jagan Teki1d150b42018-12-22 21:32:49 +053033 u32 reg;
34
Samuel Hollanda4969072022-05-09 00:29:32 -050035 if (gate && (gate->flags & CCU_CLK_F_DUMMY_GATE))
Andre Przywara2d1864f2022-05-05 01:25:43 +010036 return 0;
37
Samuel Hollanda4969072022-05-09 00:29:32 -050038 if (!gate || !(gate->flags & CCU_CLK_F_IS_VALID)) {
Jagan Teki1d150b42018-12-22 21:32:49 +053039 printf("%s: (CLK#%ld) unhandled\n", __func__, clk->id);
40 return 0;
41 }
42
43 debug("%s: (CLK#%ld) off#0x%x, BIT(%d)\n", __func__,
44 clk->id, gate->off, ilog2(gate->bit));
45
Samuel Holland90315322022-05-09 00:29:35 -050046 reg = readl(plat->base + gate->off);
Jagan Teki1d150b42018-12-22 21:32:49 +053047 if (on)
48 reg |= gate->bit;
49 else
50 reg &= ~gate->bit;
51
Samuel Holland90315322022-05-09 00:29:35 -050052 writel(reg, plat->base + gate->off);
Jagan Teki1d150b42018-12-22 21:32:49 +053053
54 return 0;
55}
56
57static int sunxi_clk_enable(struct clk *clk)
58{
59 return sunxi_set_gate(clk, true);
60}
61
62static int sunxi_clk_disable(struct clk *clk)
63{
64 return sunxi_set_gate(clk, false);
65}
66
67struct clk_ops sunxi_clk_ops = {
68 .enable = sunxi_clk_enable,
69 .disable = sunxi_clk_disable,
70};
71
Samuel Holland751c6c62022-05-09 00:29:34 -050072static int sunxi_clk_bind(struct udevice *dev)
Samuel Holland1567fdf2022-05-09 00:29:33 -050073{
Samuel Holland86b561c2022-05-09 00:29:37 -050074 /* Reuse the platform data for the reset driver. */
75 return device_bind(dev, DM_DRIVER_REF(sunxi_reset), "reset",
76 dev_get_plat(dev), dev_ofnode(dev), NULL);
Samuel Holland1567fdf2022-05-09 00:29:33 -050077}
78
Samuel Holland751c6c62022-05-09 00:29:34 -050079static int sunxi_clk_probe(struct udevice *dev)
Jagan Teki1d150b42018-12-22 21:32:49 +053080{
Andre Przywara030bab82019-01-29 15:54:08 +000081 struct clk_bulk clk_bulk;
82 struct reset_ctl_bulk rst_bulk;
83 int ret;
Jagan Teki1d150b42018-12-22 21:32:49 +053084
Andre Przywara030bab82019-01-29 15:54:08 +000085 ret = clk_get_bulk(dev, &clk_bulk);
86 if (!ret)
87 clk_enable_bulk(&clk_bulk);
88
89 ret = reset_get_bulk(dev, &rst_bulk);
90 if (!ret)
91 reset_deassert_bulk(&rst_bulk);
92
Jagan Teki1d150b42018-12-22 21:32:49 +053093 return 0;
94}
Samuel Holland751c6c62022-05-09 00:29:34 -050095
Samuel Holland90315322022-05-09 00:29:35 -050096static int sunxi_clk_of_to_plat(struct udevice *dev)
97{
98 struct ccu_plat *plat = dev_get_plat(dev);
99
100 plat->base = dev_read_addr_ptr(dev);
101 if (!plat->base)
102 return -ENOMEM;
103
104 plat->desc = (const struct ccu_desc *)dev_get_driver_data(dev);
105 if (!plat->desc)
106 return -EINVAL;
107
108 return 0;
109}
110
Samuel Holland751c6c62022-05-09 00:29:34 -0500111extern const struct ccu_desc a10_ccu_desc;
112extern const struct ccu_desc a10s_ccu_desc;
113extern const struct ccu_desc a23_ccu_desc;
114extern const struct ccu_desc a31_ccu_desc;
115extern const struct ccu_desc a31_r_ccu_desc;
116extern const struct ccu_desc a64_ccu_desc;
117extern const struct ccu_desc a80_ccu_desc;
118extern const struct ccu_desc a80_mmc_clk_desc;
119extern const struct ccu_desc a83t_ccu_desc;
Samuel Holland934d0f52022-04-30 22:38:37 -0500120extern const struct ccu_desc d1_ccu_desc;
Samuel Holland751c6c62022-05-09 00:29:34 -0500121extern const struct ccu_desc f1c100s_ccu_desc;
122extern const struct ccu_desc h3_ccu_desc;
123extern const struct ccu_desc h6_ccu_desc;
124extern const struct ccu_desc h616_ccu_desc;
Andre Przywarac0459ea2023-10-26 00:28:44 +0100125extern const struct ccu_desc a100_ccu_desc;
Samuel Holland751c6c62022-05-09 00:29:34 -0500126extern const struct ccu_desc h6_r_ccu_desc;
127extern const struct ccu_desc r40_ccu_desc;
128extern const struct ccu_desc v3s_ccu_desc;
129
130static const struct udevice_id sunxi_clk_ids[] = {
131#ifdef CONFIG_CLK_SUN4I_A10
132 { .compatible = "allwinner,sun4i-a10-ccu",
133 .data = (ulong)&a10_ccu_desc },
134#endif
135#ifdef CONFIG_CLK_SUN5I_A10S
136 { .compatible = "allwinner,sun5i-a10s-ccu",
137 .data = (ulong)&a10s_ccu_desc },
138 { .compatible = "allwinner,sun5i-a13-ccu",
139 .data = (ulong)&a10s_ccu_desc },
140#endif
141#ifdef CONFIG_CLK_SUN6I_A31
142 { .compatible = "allwinner,sun6i-a31-ccu",
143 .data = (ulong)&a31_ccu_desc },
144#endif
145#ifdef CONFIG_CLK_SUN4I_A10
146 { .compatible = "allwinner,sun7i-a20-ccu",
147 .data = (ulong)&a10_ccu_desc },
148#endif
149#ifdef CONFIG_CLK_SUN8I_A23
150 { .compatible = "allwinner,sun8i-a23-ccu",
151 .data = (ulong)&a23_ccu_desc },
152 { .compatible = "allwinner,sun8i-a33-ccu",
153 .data = (ulong)&a23_ccu_desc },
154#endif
155#ifdef CONFIG_CLK_SUN8I_A83T
156 { .compatible = "allwinner,sun8i-a83t-ccu",
157 .data = (ulong)&a83t_ccu_desc },
158#endif
159#ifdef CONFIG_CLK_SUN6I_A31_R
160 { .compatible = "allwinner,sun8i-a83t-r-ccu",
161 .data = (ulong)&a31_r_ccu_desc },
162#endif
163#ifdef CONFIG_CLK_SUN8I_H3
164 { .compatible = "allwinner,sun8i-h3-ccu",
165 .data = (ulong)&h3_ccu_desc },
166#endif
167#ifdef CONFIG_CLK_SUN6I_A31_R
168 { .compatible = "allwinner,sun8i-h3-r-ccu",
169 .data = (ulong)&a31_r_ccu_desc },
170#endif
171#ifdef CONFIG_CLK_SUN8I_R40
172 { .compatible = "allwinner,sun8i-r40-ccu",
173 .data = (ulong)&r40_ccu_desc },
174#endif
175#ifdef CONFIG_CLK_SUN8I_V3S
176 { .compatible = "allwinner,sun8i-v3-ccu",
177 .data = (ulong)&v3s_ccu_desc },
178 { .compatible = "allwinner,sun8i-v3s-ccu",
179 .data = (ulong)&v3s_ccu_desc },
180#endif
181#ifdef CONFIG_CLK_SUN9I_A80
182 { .compatible = "allwinner,sun9i-a80-ccu",
183 .data = (ulong)&a80_ccu_desc },
184 { .compatible = "allwinner,sun9i-a80-mmc-config-clk",
185 .data = (ulong)&a80_mmc_clk_desc },
186#endif
187#ifdef CONFIG_CLK_SUN50I_A64
188 { .compatible = "allwinner,sun50i-a64-ccu",
189 .data = (ulong)&a64_ccu_desc },
190#endif
191#ifdef CONFIG_CLK_SUN6I_A31_R
192 { .compatible = "allwinner,sun50i-a64-r-ccu",
193 .data = (ulong)&a31_r_ccu_desc },
194#endif
195#ifdef CONFIG_CLK_SUN8I_H3
196 { .compatible = "allwinner,sun50i-h5-ccu",
197 .data = (ulong)&h3_ccu_desc },
198#endif
Samuel Holland934d0f52022-04-30 22:38:37 -0500199#ifdef CONFIG_CLK_SUN20I_D1
200 { .compatible = "allwinner,sun20i-d1-ccu",
201 .data = (ulong)&d1_ccu_desc },
202#endif
Samuel Holland751c6c62022-05-09 00:29:34 -0500203#ifdef CONFIG_CLK_SUN50I_H6
204 { .compatible = "allwinner,sun50i-h6-ccu",
205 .data = (ulong)&h6_ccu_desc },
206#endif
207#ifdef CONFIG_CLK_SUN50I_H6_R
208 { .compatible = "allwinner,sun50i-h6-r-ccu",
209 .data = (ulong)&h6_r_ccu_desc },
210#endif
211#ifdef CONFIG_CLK_SUN50I_H616
212 { .compatible = "allwinner,sun50i-h616-ccu",
213 .data = (ulong)&h616_ccu_desc },
214#endif
215#ifdef CONFIG_CLK_SUN50I_H6_R
216 { .compatible = "allwinner,sun50i-h616-r-ccu",
217 .data = (ulong)&h6_r_ccu_desc },
218#endif
Andre Przywarac0459ea2023-10-26 00:28:44 +0100219#ifdef CONFIG_CLK_SUN50I_A100
220 { .compatible = "allwinner,sun50i-a100-ccu",
221 .data = (ulong)&a100_ccu_desc },
222#endif
Samuel Holland751c6c62022-05-09 00:29:34 -0500223#ifdef CONFIG_CLK_SUNIV_F1C100S
224 { .compatible = "allwinner,suniv-f1c100s-ccu",
225 .data = (ulong)&f1c100s_ccu_desc },
226#endif
227 { }
228};
229
230U_BOOT_DRIVER(sunxi_clk) = {
231 .name = "sunxi_clk",
232 .id = UCLASS_CLK,
233 .of_match = sunxi_clk_ids,
234 .bind = sunxi_clk_bind,
235 .probe = sunxi_clk_probe,
Samuel Holland90315322022-05-09 00:29:35 -0500236 .of_to_plat = sunxi_clk_of_to_plat,
237 .plat_auto = sizeof(struct ccu_plat),
Samuel Holland751c6c62022-05-09 00:29:34 -0500238 .ops = &sunxi_clk_ops,
239};