TracyMg_Li | 734d577 | 2023-12-25 11:21:34 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2023, Phytium Technology Co., Ltd. |
| 4 | * lixinde <lixinde@phytium.com.cn> |
| 5 | * weichangzheng <weichangzheng@phytium.com.cn> |
| 6 | */ |
| 7 | |
| 8 | #include <stdio.h> |
| 9 | #include <command.h> |
| 10 | #include <init.h> |
| 11 | #include <asm/armv8/mmu.h> |
| 12 | #include <asm/io.h> |
| 13 | #include <linux/arm-smccc.h> |
| 14 | #include <scsi.h> |
| 15 | #include <asm/u-boot.h> |
| 16 | #include "cpu.h" |
| 17 | |
| 18 | DECLARE_GLOBAL_DATA_PTR; |
| 19 | |
| 20 | int mach_cpu_init(void) |
| 21 | { |
| 22 | check_reset(); |
| 23 | return 0; |
| 24 | } |
| 25 | |
| 26 | int board_early_init_f(void) |
| 27 | { |
| 28 | pcie_init(); |
| 29 | return 0; |
| 30 | } |
| 31 | |
| 32 | int dram_init(void) |
| 33 | { |
| 34 | debug("Phytium ddr init\n"); |
| 35 | ddr_init(); |
| 36 | |
| 37 | gd->mem_clk = 0; |
| 38 | gd->ram_size = PHYS_SDRAM_1_SIZE; |
| 39 | |
| 40 | sec_init(); |
| 41 | debug("PBF relocate done\n"); |
| 42 | |
| 43 | return 0; |
| 44 | } |
| 45 | |
| 46 | int dram_init_banksize(void) |
| 47 | { |
| 48 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
| 49 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
| 50 | |
| 51 | return 0; |
| 52 | } |
| 53 | |
| 54 | int board_init(void) |
| 55 | { |
| 56 | return 0; |
| 57 | } |
| 58 | |
| 59 | void reset_cpu(void) |
| 60 | { |
| 61 | struct arm_smccc_res res; |
| 62 | |
| 63 | debug("run in reset cpu\n"); |
| 64 | arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res); |
| 65 | if (res.a0 != 0) |
| 66 | panic("reset cpu error, %lx\n", res.a0); |
| 67 | } |
| 68 | |
| 69 | static struct mm_region pe2201_mem_map[] = { |
| 70 | { |
| 71 | .virt = 0x0UL, |
| 72 | .phys = 0x0UL, |
| 73 | .size = 0x80000000UL, |
| 74 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN |
| 75 | }, |
| 76 | { |
| 77 | .virt = 0x80000000UL, |
| 78 | .phys = 0x80000000UL, |
| 79 | .size = 0x7b000000UL, |
| 80 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NS | PTE_BLOCK_INNER_SHARE |
| 81 | }, |
| 82 | { |
| 83 | 0, |
| 84 | } |
| 85 | }; |
| 86 | |
| 87 | struct mm_region *mem_map = pe2201_mem_map; |
| 88 | |
| 89 | int last_stage_init(void) |
| 90 | { |
| 91 | return 0; |
| 92 | } |