| Simon Glass | 98d88f8 | 2019-02-16 20:24:49 -0700 | [diff] [blame] | 1 | config PCH |
| 2 | bool "Enable Platform-controller Hub (PCH) support" |
| 3 | depends on X86 || SANDBOX |
| 4 | help |
| 5 | Most x86 chips include a PCH which is responsible for handling |
| 6 | parts of the system not handled by that CPU. It supersedes the |
| 7 | northbridge / southbridge architecture that was previously used. The |
| 8 | PCH allows for higher performance since the memory functions are |
| 9 | handled in the CPU. |
| Simon Glass | c01f4f0 | 2019-12-06 21:42:14 -0700 | [diff] [blame^] | 10 | |
| 11 | config X86_PCH7 |
| 12 | bool "Add support for Intel PCH7" |
| 13 | default y if X86 |
| 14 | help |
| 15 | Enable this if your SoC uses Platform Controller Hub 7 (PCH7). This |
| 16 | dates from about 2011 and is used on baytrail, for example. The |
| 17 | PCH provides access to the GPIO and SPI base addresses, among other |
| 18 | functions. |
| 19 | |
| 20 | config X86_PCH9 |
| 21 | bool "Add support for Intel PCH9" |
| 22 | default y if X86 |
| 23 | help |
| 24 | Enable this if your SoC uses Platform Controller Hub 9 (PCH9). This |
| 25 | dates from about 2015 and is used on baytrail, for example. The |
| 26 | PCH provides access to the GPIO and SPI base addresses, among other |
| 27 | functions. |