blob: 71078e99806e4e8e94f812c7d0a1cf04ca6f0151 [file] [log] [blame]
Heiko Schocher499c4982013-08-19 16:39:01 +02001/*
2 * siemens rut
3 * (C) Copyright 2013 Siemens Schweiz AG
4 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 *
6 * Based on:
7 * U-Boot file:/include/configs/am335x_evm.h
8 *
9 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
10 *
11 * SPDX-License-Identifier: GPL-2.0+
12 */
13
14#ifndef __CONFIG_RUT_H
15#define __CONFIG_RUT_H
16
17#define CONFIG_SIEMENS_RUT
Heiko Schocher499c4982013-08-19 16:39:01 +020018#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_RUT
19
20#include "siemens-am33x-common.h"
21
Heiko Schocher499c4982013-08-19 16:39:01 +020022#define RUT_IOCTRL_VAL 0x18b
23#define DDR_PLL_FREQ 303
24
25 /* Physical Memory Map */
26#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MiB */
27
28/* I2C Configuration */
29#define CONFIG_SYS_I2C_SPEED 100000
30
31#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
32#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
33#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
34#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
35
Heiko Schocher499c4982013-08-19 16:39:01 +020036#define CONFIG_PHY_NATSEMI
37
38#define CONFIG_FACTORYSET
39
Heiko Schocher499c4982013-08-19 16:39:01 +020040/* Watchdog */
41#define WATCHDOG_TRIGGER_GPIO 14
42
43#ifndef CONFIG_SPL_BUILD
44
Heiko Schocherd17c3fc2015-06-16 14:59:34 +020045/* Use common default */
Heiko Schocherd17c3fc2015-06-16 14:59:34 +020046
Heiko Schocher499c4982013-08-19 16:39:01 +020047/* Default env settings */
48#define CONFIG_EXTRA_ENV_SETTINGS \
49 "hostname=rut\0" \
Heiko Schochercbec11a2016-06-07 08:55:45 +020050 "ubi_off=2048\0"\
Samuel Egli8069bfe2013-11-04 14:05:03 +010051 "nand_img_size=0x500000\0" \
52 "splashpos=m,m\0" \
Heiko Schocher499c4982013-08-19 16:39:01 +020053 "optargs=fixrtc --no-log consoleblank=0 \0" \
Heiko Schocherd17c3fc2015-06-16 14:59:34 +020054 CONFIG_ENV_SETTINGS_V1 \
55 CONFIG_ENV_SETTINGS_NAND_V1 \
Heiko Schocher499c4982013-08-19 16:39:01 +020056 "mmc_dev=0\0" \
57 "mmc_root=/dev/mmcblk0p2 rw\0" \
58 "mmc_root_fs_type=ext4 rootwait\0" \
59 "mmc_load_uimage=" \
60 "mmc rescan; " \
61 "setenv bootfile uImage;" \
62 "fatload mmc ${mmc_dev} ${kloadaddr} ${bootfile}\0" \
63 "loadbootenv=fatload mmc ${mmc_dev} ${loadaddr} ${bootenv}\0" \
64 "importbootenv=echo Importing environment from mmc ...; " \
65 "env import -t $loadaddr $filesize\0" \
66 "mmc_args=run bootargs_defaults;" \
67 "mtdparts default;" \
68 "setenv bootargs ${bootargs} " \
69 "root=${mmc_root} ${mtdparts}" \
70 "rootfstype=${mmc_root_fs_type} ip=${ip_method} " \
71 "eth=${ethaddr} " \
72 "\0" \
73 "mmc_boot=run mmc_args; " \
74 "run mmc_load_uimage; " \
75 "bootm ${kloadaddr}\0" \
76 ""
77
78#ifndef CONFIG_RESTORE_FLASH
79/* set to negative value for no autoboot */
Heiko Schocher499c4982013-08-19 16:39:01 +020080
81#define CONFIG_BOOTCOMMAND \
82 "if mmc rescan; then " \
83 "echo SD/MMC found on device ${mmc_dev};" \
84 "if run loadbootenv; then " \
85 "echo Loaded environment from ${bootenv};" \
86 "run importbootenv;" \
87 "fi;" \
88 "if test -n $uenvcmd; then " \
89 "echo Running uenvcmd ...;" \
90 "run uenvcmd;" \
91 "fi;" \
92 "if run mmc_load_uimage; then " \
93 "run mmc_args;" \
94 "bootm ${kloadaddr};" \
95 "fi;" \
96 "fi;" \
97 "run nand_boot;" \
Samuel Egli8069bfe2013-11-04 14:05:03 +010098 "reset;"
Heiko Schocher499c4982013-08-19 16:39:01 +020099
100#else
Heiko Schocher499c4982013-08-19 16:39:01 +0200101
102#define CONFIG_BOOTCOMMAND \
103 "setenv autoload no; " \
104 "dhcp; " \
105 "if tftp 80000000 debrick.scr; then " \
106 "source 80000000; " \
107 "fi"
108#endif
109
110#endif /* CONFIG_SPL_BUILD */
111
Heiko Schocher499c4982013-08-19 16:39:01 +0200112#if defined(CONFIG_VIDEO)
113#define CONFIG_VIDEO_DA8XX
Heiko Schocher499c4982013-08-19 16:39:01 +0200114#define CONFIG_SPLASH_SCREEN
115#define CONFIG_SPLASH_SCREEN_ALIGN
116#define CONFIG_VIDEO_LOGO
117#define CONFIG_VIDEO_BMP_RLE8
118#define CONFIG_VIDEO_BMP_LOGO
Heiko Schocher499c4982013-08-19 16:39:01 +0200119#define DA8XX_LCD_CNTL_BASE LCD_CNTL_BASE
120
121#define CONFIG_SPI
Heiko Schocher499c4982013-08-19 16:39:01 +0200122
123#define BOARD_LCD_RESET 115 /* Bank 3 pin 19 */
Heiko Schocher499c4982013-08-19 16:39:01 +0200124#define CONFIG_FORMIKE
Samuel Egli8069bfe2013-11-04 14:05:03 +0100125#define DISPL_PLL_SPREAD_SPECTRUM
Heiko Schocher499c4982013-08-19 16:39:01 +0200126#endif
127
Heiko Schocher499c4982013-08-19 16:39:01 +0200128#endif /* ! __CONFIG_RUT_H */