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git01.mediatek.com / filogic / uboot / c008690087698ef6713e6c92d0e68d8896043094 / . / arch / arm / dts / nuvoton-common-npcm8xx.dtsi
blob: fabe5925b70711025fa87f1d635835edb76bb12d [file] [log] [blame]
Jim Liu147c0002022-09-27 16:45:15 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
3
4#include <dt-bindings/clock/nuvoton,npcm845-clk.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/interrupt-controller/irq.h>
Jim Liu89b26542022-11-28 10:32:44 +0800[diff] [blame]7#include <dt-bindings/gpio/gpio.h>
Jim Liu147c0002022-09-27 16:45:15 +0800[diff] [blame]8
9/ {
10 #address-cells = <2>;
11 #size-cells = <2>;
12 interrupt-parent = <&gic>;
13
14 soc {
15 #address-cells = <2>;
16 #size-cells = <2>;
17 compatible = "simple-bus";
18 interrupt-parent = <&gic>;
19 ranges;
20
21 gcr: system-controller@f0800000 {
22 compatible = "nuvoton,npcm845-gcr", "syscon";
23 reg = <0x0 0xf0800000 0x0 0x1000>;
24 };
25
26 gic: interrupt-controller@dfff9000 {
27 compatible = "arm,gic-400";
28 reg = <0x0 0xdfff9000 0x0 0x1000>,
29 <0x0 0xdfffa000 0x0 0x2000>,
30 <0x0 0xdfffc000 0x0 0x2000>,
31 <0x0 0xdfffe000 0x0 0x2000>;
32 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
33 #interrupt-cells = <3>;
34 interrupt-controller;
35 #address-cells = <0>;
36 ppi-partitions {
37 ppi_cluster0: interrupt-partition-0 {
38 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
39 };
40 };
41 };
42 };
43
44 ahb {
45 #address-cells = <2>;
46 #size-cells = <2>;
47 compatible = "simple-bus";
48 interrupt-parent = <&gic>;
49 ranges;
50
51 rstc: reset-controller@f0801000 {
52 compatible = "nuvoton,npcm845-reset";
53 reg = <0x0 0xf0801000 0x0 0x78>;
54 #reset-cells = <2>;
55 nuvoton,sysgcr = <&gcr>;
56 };
57
58 clk: clock-controller@f0801000 {
59 compatible = "nuvoton,npcm845-clk";
60 #clock-cells = <1>;
61 reg = <0x0 0xf0801000 0x0 0x1000>;
62 };
63
Jim Liu89b26542022-11-28 10:32:44 +0800[diff] [blame]64 sdhci0: sdhci@f0842000 {
65 compatible = "nuvoton,npcm845-sdhci";
66 reg = <0x0 0xf0842000 0x0 0x100>;
67 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
68 clocks = <&clk NPCM8XX_CLK_AHB>;
69 clock-names = "clk_mmc";
70 pinctrl-names = "default";
71 pinctrl-0 = <&mmc8_pins
72 &mmc_pins>;
73 status = "disabled";
74 };
75
76 fiu0: spi@fb000000 {
77 compatible = "nuvoton,npcm845-fiu";
78 #address-cells = <1>;
79 #size-cells = <0>;
80 reg = <0x0 0xfb000000 0x0 0x1000>,
81 <0x0 0x80000000 0x0 0x10000000>;
82 reg-names = "control", "memory";
83 clocks = <&clk NPCM8XX_CLK_SPI0>;
84 clock-names = "clk_ahb";
85 status = "disabled";
86 };
87
88 fiu1: spi@fb002000 {
89 compatible = "nuvoton,npcm845-fiu";
90 #address-cells = <1>;
91 #size-cells = <0>;
92 reg = <0x0 0xfb002000 0x0 0x1000>,
93 <0x0 0x90000000 0x0 0x4000000>;
94 reg-names = "control", "memory";
95 clocks = <&clk NPCM8XX_CLK_SPI1>;
96 clock-names = "clk_spi1";
97 pinctrl-names = "default";
98 pinctrl-0 = <&spi1_pins>;
99 status = "disabled";
100 };
101
102 fiu3: spi@c0000000 {
103 compatible = "nuvoton,npcm845-fiu";
104 #address-cells = <1>;
105 #size-cells = <0>;
106 reg = <0x0 0xc0000000 0x0 0x1000>,
107 <0x0 0xA0000000 0x0 0x20000000>;
108 reg-names = "control", "memory";
109 clocks = <&clk NPCM8XX_CLK_SPI3>;
110 clock-names = "clk_spi3";
111 pinctrl-names = "default";
112 pinctrl-0 = <&spi3_pins>;
113 status = "disabled";
114 };
115
116 fiux: spi@fb001000 {
117 compatible = "nuvoton,npcm845-fiu";
118 #address-cells = <1>;
119 #size-cells = <0>;
120 reg = <0x0 0xfb001000 0x0 0x1000>,
121 <0x0 0xf8000000 0x0 0x2000000>;
122 reg-names = "control", "memory";
123 clocks = <&clk NPCM8XX_CLK_SPIX>;
124 clock-names = "clk_ahb";
125 status = "disabled";
126 };
127
Jim Liu147c0002022-09-27 16:45:15 +0800[diff] [blame]128 apb {
129 #address-cells = <1>;
130 #size-cells = <1>;
131 compatible = "simple-bus";
132 interrupt-parent = <&gic>;
133 ranges = <0x0 0x0 0xf0000000 0x00300000>,
134 <0xfff00000 0x0 0xfff00000 0x00016000>;
135
Jim Liu89b26542022-11-28 10:32:44 +0800[diff] [blame]136 spi1: spi@201000 {
137 compatible = "nuvoton,npcm845-pspi";
138 reg = <0x201000 0x1000>;
139 pinctrl-names = "default";
140 pinctrl-0 = <&pspi_pins>;
141 #address-cells = <1>;
142 #size-cells = <0>;
143 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
144 clocks = <&clk NPCM8XX_CLK_APB5>;
145 clock-names = "clk_apb5";
146 status = "disabled";
147 };
148
Jim Liu147c0002022-09-27 16:45:15 +0800[diff] [blame]149 timer0: timer@8000 {
150 compatible = "nuvoton,npcm845-timer";
151 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
152 reg = <0x8000 0x1C>;
153 clocks = <&clk NPCM8XX_CLK_REFCLK>;
154 clock-names = "refclk";
155 };
156
157 serial0: serial@0 {
158 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
159 reg = <0x0 0x1000>;
160 clocks = <&clk NPCM8XX_CLK_UART>;
161 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
162 reg-shift = <2>;
163 status = "disabled";
164 };
165
166 serial1: serial@1000 {
167 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
168 reg = <0x1000 0x1000>;
169 clocks = <&clk NPCM8XX_CLK_UART>;
170 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
171 reg-shift = <2>;
172 status = "disabled";
173 };
174
175 serial2: serial@2000 {
176 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
177 reg = <0x2000 0x1000>;
178 clocks = <&clk NPCM8XX_CLK_UART>;
179 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
180 reg-shift = <2>;
181 status = "disabled";
182 };
183
184 serial3: serial@3000 {
185 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
186 reg = <0x3000 0x1000>;
187 clocks = <&clk NPCM8XX_CLK_UART>;
188 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
189 reg-shift = <2>;
190 status = "disabled";
191 };
192
193 serial4: serial@4000 {
194 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
195 reg = <0x4000 0x1000>;
196 clocks = <&clk NPCM8XX_CLK_UART>;
197 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
198 reg-shift = <2>;
199 status = "disabled";
200 };
201
202 serial5: serial@5000 {
203 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
204 reg = <0x5000 0x1000>;
205 clocks = <&clk NPCM8XX_CLK_UART>;
206 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
207 reg-shift = <2>;
208 status = "disabled";
209 };
210
211 serial6: serial@6000 {
212 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
213 reg = <0x6000 0x1000>;
214 clocks = <&clk NPCM8XX_CLK_UART>;
215 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
216 reg-shift = <2>;
217 status = "disabled";
218 };
219
220 watchdog0: watchdog@801c {
221 compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
222 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
223 reg = <0x801c 0x4>;
224 status = "disabled";
225 clocks = <&clk NPCM8XX_CLK_REFCLK>;
226 syscon = <&gcr>;
227 };
228
229 watchdog1: watchdog@901c {
230 compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
231 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
232 reg = <0x901c 0x4>;
233 status = "disabled";
234 clocks = <&clk NPCM8XX_CLK_REFCLK>;
235 syscon = <&gcr>;
236 };
237
238 watchdog2: watchdog@a01c {
239 compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
240 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
241 reg = <0xa01c 0x4>;
242 status = "disabled";
243 clocks = <&clk NPCM8XX_CLK_REFCLK>;
244 syscon = <&gcr>;
245 };
Jim Liu89b26542022-11-28 10:32:44 +0800[diff] [blame]246
247 i2c0: i2c@80000 {
248 compatible = "nuvoton,npcm845-i2c";
249 reg = <0x80000 0x1000>;
250 #address-cells = <1>;
251 #size-cells = <0>;
252 clocks = <&clk NPCM8XX_CLK_APB2>;
253 clock-frequency = <100000>;
254 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
255 pinctrl-names = "default";
256 pinctrl-0 = <&smb0_pins>;
257 syscon = <&gcr>;
258 status = "disabled";
259 };
Jim Liu2e4fb4e2023-01-17 16:59:21 +0800[diff] [blame]260
261 i2c1: i2c@81000 {
262 compatible = "nuvoton,npcm845-i2c";
263 reg = <0x81000 0x1000>;
264 #address-cells = <1>;
265 #size-cells = <0>;
266 clocks = <&clk NPCM8XX_CLK_APB2>;
267 clock-frequency = <100000>;
268 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
269 pinctrl-names = "default";
270 pinctrl-0 = <&smb1_pins>;
271 syscon = <&gcr>;
272 status = "disabled";
273 };
274
275 i2c2: i2c@82000 {
276 compatible = "nuvoton,npcm845-i2c";
277 reg = <0x82000 0x1000>;
278 #address-cells = <1>;
279 #size-cells = <0>;
280 clocks = <&clk NPCM8XX_CLK_APB2>;
281 clock-frequency = <100000>;
282 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
283 pinctrl-names = "default";
284 pinctrl-0 = <&smb2_pins>;
285 syscon = <&gcr>;
286 status = "disabled";
287 };
288
289 i2c3: i2c@83000 {
290 compatible = "nuvoton,npcm845-i2c";
291 reg = <0x83000 0x1000>;
292 #address-cells = <1>;
293 #size-cells = <0>;
294 clocks = <&clk NPCM8XX_CLK_APB2>;
295 clock-frequency = <100000>;
296 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
297 pinctrl-names = "default";
298 pinctrl-0 = <&smb3_pins>;
299 syscon = <&gcr>;
300 status = "disabled";
301 };
302
303 i2c4: i2c@84000 {
304 compatible = "nuvoton,npcm845-i2c";
305 reg = <0x84000 0x1000>;
306 #address-cells = <1>;
307 #size-cells = <0>;
308 clocks = <&clk NPCM8XX_CLK_APB2>;
309 clock-frequency = <100000>;
310 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
311 pinctrl-names = "default";
312 pinctrl-0 = <&smb4_pins>;
313 syscon = <&gcr>;
314 status = "disabled";
315 };
316
317 i2c5: i2c@85000 {
318 compatible = "nuvoton,npcm845-i2c";
319 reg = <0x85000 0x1000>;
320 #address-cells = <1>;
321 #size-cells = <0>;
322 clocks = <&clk NPCM8XX_CLK_APB2>;
323 clock-frequency = <100000>;
324 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
325 pinctrl-names = "default";
326 pinctrl-0 = <&smb5_pins>;
327 syscon = <&gcr>;
328 status = "disabled";
329 };
330
331 i2c6: i2c@86000 {
332 compatible = "nuvoton,npcm845-i2c";
333 reg = <0x86000 0x1000>;
334 #address-cells = <1>;
335 #size-cells = <0>;
336 clocks = <&clk NPCM8XX_CLK_APB2>;
337 clock-frequency = <100000>;
338 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
339 pinctrl-names = "default";
340 pinctrl-0 = <&smb6_pins>;
341 syscon = <&gcr>;
342 status = "disabled";
343 };
344
345 i2c7: i2c@87000 {
346 compatible = "nuvoton,npcm845-i2c";
347 reg = <0x87000 0x1000>;
348 #address-cells = <1>;
349 #size-cells = <0>;
350 clocks = <&clk NPCM8XX_CLK_APB2>;
351 clock-frequency = <100000>;
352 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
353 pinctrl-names = "default";
354 pinctrl-0 = <&smb7_pins>;
355 syscon = <&gcr>;
356 status = "disabled";
357 };
358
359 i2c8: i2c@88000 {
360 compatible = "nuvoton,npcm845-i2c";
361 reg = <0x88000 0x1000>;
362 #address-cells = <1>;
363 #size-cells = <0>;
364 clocks = <&clk NPCM8XX_CLK_APB2>;
365 clock-frequency = <100000>;
366 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
367 pinctrl-names = "default";
368 pinctrl-0 = <&smb8_pins>;
369 syscon = <&gcr>;
370 status = "disabled";
371 };
372
373 i2c9: i2c@89000 {
374 compatible = "nuvoton,npcm845-i2c";
375 reg = <0x89000 0x1000>;
376 #address-cells = <1>;
377 #size-cells = <0>;
378 clocks = <&clk NPCM8XX_CLK_APB2>;
379 clock-frequency = <100000>;
380 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
381 pinctrl-names = "default";
382 pinctrl-0 = <&smb9_pins>;
383 syscon = <&gcr>;
384 status = "disabled";
385 };
386
387 i2c10: i2c@8a000 {
388 compatible = "nuvoton,npcm845-i2c";
389 reg = <0x8a000 0x1000>;
390 #address-cells = <1>;
391 #size-cells = <0>;
392 clocks = <&clk NPCM8XX_CLK_APB2>;
393 clock-frequency = <100000>;
394 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
395 pinctrl-names = "default";
396 pinctrl-0 = <&smb10_pins>;
397 syscon = <&gcr>;
398 status = "disabled";
399 };
400
401 i2c11: i2c@8b000 {
402 compatible = "nuvoton,npcm845-i2c";
403 reg = <0x8b000 0x1000>;
404 #address-cells = <1>;
405 #size-cells = <0>;
406 clocks = <&clk NPCM8XX_CLK_APB2>;
407 clock-frequency = <100000>;
408 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
409 pinctrl-names = "default";
410 pinctrl-0 = <&smb11_pins>;
411 syscon = <&gcr>;
412 status = "disabled";
413 };
414
415 i2c12: i2c@8c000 {
416 compatible = "nuvoton,npcm845-i2c";
417 reg = <0x8c000 0x1000>;
418 #address-cells = <1>;
419 #size-cells = <0>;
420 clocks = <&clk NPCM8XX_CLK_APB2>;
421 clock-frequency = <100000>;
422 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
423 pinctrl-names = "default";
424 pinctrl-0 = <&smb12_pins>;
425 syscon = <&gcr>;
426 status = "disabled";
427 };
428
429 i2c13: i2c@8d000 {
430 compatible = "nuvoton,npcm845-i2c";
431 reg = <0x8d000 0x1000>;
432 #address-cells = <1>;
433 #size-cells = <0>;
434 clocks = <&clk NPCM8XX_CLK_APB2>;
435 clock-frequency = <100000>;
436 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
437 pinctrl-names = "default";
438 pinctrl-0 = <&smb13_pins>;
439 syscon = <&gcr>;
440 status = "disabled";
441 };
442
443 i2c14: i2c@8e000 {
444 compatible = "nuvoton,npcm845-i2c";
445 reg = <0x8e000 0x1000>;
446 #address-cells = <1>;
447 #size-cells = <0>;
448 clocks = <&clk NPCM8XX_CLK_APB2>;
449 clock-frequency = <100000>;
450 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
451 pinctrl-names = "default";
452 pinctrl-0 = <&smb14_pins>;
453 syscon = <&gcr>;
454 status = "disabled";
455 };
456
457 i2c15: i2c@8f000 {
458 compatible = "nuvoton,npcm845-i2c";
459 reg = <0x8f000 0x1000>;
460 #address-cells = <1>;
461 #size-cells = <0>;
462 clocks = <&clk NPCM8XX_CLK_APB2>;
463 clock-frequency = <100000>;
464 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&smb15_pins>;
467 syscon = <&gcr>;
468 status = "disabled";
469 };
470
471 i2c16: i2c@fff00000 {
472 compatible = "nuvoton,npcm845-i2c";
473 reg = <0xfff00000 0x1000>;
474 #address-cells = <1>;
475 #size-cells = <0>;
476 clocks = <&clk NPCM8XX_CLK_APB2>;
477 clock-frequency = <100000>;
478 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
479 pinctrl-names = "default";
480 pinctrl-0 = <&smb16_pins>;
481 syscon = <&gcr>;
482 status = "disabled";
483 };
484
485 i2c17: i2c@fff01000 {
486 compatible = "nuvoton,npcm845-i2c";
487 reg = <0xfff01000 0x1000>;
488 #address-cells = <1>;
489 #size-cells = <0>;
490 clocks = <&clk NPCM8XX_CLK_APB2>;
491 clock-frequency = <100000>;
492 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
493 pinctrl-names = "default";
494 pinctrl-0 = <&smb17_pins>;
495 syscon = <&gcr>;
496 status = "disabled";
497 };
498
499 i2c18: i2c@fff02000 {
500 compatible = "nuvoton,npcm845-i2c";
501 reg = <0xfff02000 0x1000>;
502 #address-cells = <1>;
503 #size-cells = <0>;
504 clocks = <&clk NPCM8XX_CLK_APB2>;
505 clock-frequency = <100000>;
506 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
507 pinctrl-names = "default";
508 pinctrl-0 = <&smb18_pins>;
509 syscon = <&gcr>;
510 status = "disabled";
511 };
512
513 i2c19: i2c@fff03000 {
514 compatible = "nuvoton,npcm845-i2c";
515 reg = <0xfff03000 0x1000>;
516 #address-cells = <1>;
517 #size-cells = <0>;
518 clocks = <&clk NPCM8XX_CLK_APB2>;
519 clock-frequency = <100000>;
520 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
521 pinctrl-names = "default";
522 pinctrl-0 = <&smb19_pins>;
523 syscon = <&gcr>;
524 status = "disabled";
525 };
526
527 i2c20: i2c@fff04000 {
528 compatible = "nuvoton,npcm845-i2c";
529 reg = <0xfff04000 0x1000>;
530 #address-cells = <1>;
531 #size-cells = <0>;
532 clocks = <&clk NPCM8XX_CLK_APB2>;
533 clock-frequency = <100000>;
534 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
535 pinctrl-names = "default";
536 pinctrl-0 = <&smb20_pins>;
537 syscon = <&gcr>;
538 status = "disabled";
539 };
540
541 i2c21: i2c@fff05000 {
542 compatible = "nuvoton,npcm845-i2c";
543 reg = <0xfff05000 0x1000>;
544 #address-cells = <1>;
545 #size-cells = <0>;
546 clocks = <&clk NPCM8XX_CLK_APB2>;
547 clock-frequency = <100000>;
548 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
549 pinctrl-names = "default";
550 pinctrl-0 = <&smb21_pins>;
551 syscon = <&gcr>;
552 status = "disabled";
553 };
554
555 i2c22: i2c@fff06000 {
556 compatible = "nuvoton,npcm845-i2c";
557 reg = <0xfff06000 0x1000>;
558 #address-cells = <1>;
559 #size-cells = <0>;
560 clocks = <&clk NPCM8XX_CLK_APB2>;
561 clock-frequency = <100000>;
562 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
563 pinctrl-names = "default";
564 pinctrl-0 = <&smb22_pins>;
565 syscon = <&gcr>;
566 status = "disabled";
567 };
568
569 i2c23: i2c@fff07000 {
570 compatible = "nuvoton,npcm845-i2c";
571 reg = <0xfff07000 0x1000>;
572 #address-cells = <1>;
573 #size-cells = <0>;
574 clocks = <&clk NPCM8XX_CLK_APB2>;
575 clock-frequency = <100000>;
576 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
577 pinctrl-names = "default";
578 pinctrl-0 = <&smb23_pins>;
579 syscon = <&gcr>;
580 status = "disabled";
581 };
582
583 i2c24: i2c@fff08000 {
584 compatible = "nuvoton,npcm845-i2c";
585 reg = <0xfff08000 0x1000>;
586 #address-cells = <1>;
587 #size-cells = <0>;
588 clocks = <&clk NPCM8XX_CLK_APB2>;
589 clock-frequency = <100000>;
590 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
591 syscon = <&gcr>;
592 status = "disabled";
593 };
594
595 i2c25: i2c@fff09000 {
596 compatible = "nuvoton,npcm845-i2c";
597 reg = <0xfff09000 0x1000>;
598 #address-cells = <1>;
599 #size-cells = <0>;
600 clocks = <&clk NPCM8XX_CLK_APB2>;
601 clock-frequency = <100000>;
602 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
603 syscon = <&gcr>;
604 status = "disabled";
605 };
606
607 i2c26: i2c@fff0a000 {
608 compatible = "nuvoton,npcm845-i2c";
609 reg = <0xfff0a000 0x1000>;
610 #address-cells = <1>;
611 #size-cells = <0>;
612 clocks = <&clk NPCM8XX_CLK_APB2>;
613 clock-frequency = <100000>;
614 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
615 syscon = <&gcr>;
616 status = "disabled";
617 };
Jim Liu147c0002022-09-27 16:45:15 +0800[diff] [blame]618 };
619 };
620};