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git01.mediatek.com / filogic / uboot / c008690087698ef6713e6c92d0e68d8896043094 / . / arch / arm / dts / mt7988.dtsi
blob: ac476d5cdd7f85c23d35596ff884dbdc81884bb7 [file] [log] [blame]
developerf596c1a2023-07-19 17:17:49 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/mt7988-clk.h>
10#include <dt-bindings/reset/mt7988-reset.h>
11#include <dt-bindings/gpio/gpio.h>
Frank Wunderlich7950d172023-08-03 20:00:01 +0200[diff] [blame]12#include <dt-bindings/phy/phy.h>
developerf596c1a2023-07-19 17:17:49 +0800[diff] [blame]13
14/ {
15 compatible = "mediatek,mt7988-rfb";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 cpu0: cpu@0 {
25 device_type = "cpu";
26 compatible = "arm,cortex-a73";
27 reg = <0x0>;
28 mediatek,hwver = <&hwver>;
29 };
30
31 cpu1: cpu@1 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a73";
34 reg = <0x1>;
35 mediatek,hwver = <&hwver>;
36 };
37
38 cpu2: cpu@2 {
39 device_type = "cpu";
40 compatible = "arm,cortex-a73";
41 reg = <0x2>;
42 mediatek,hwver = <&hwver>;
43 };
44
45 cpu3: cpu@3 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a73";
48 reg = <0x3>;
49 mediatek,hwver = <&hwver>;
50 };
51 };
52
53 system_clk: dummy40m {
54 compatible = "fixed-clock";
55 clock-frequency = <40000000>;
56 #clock-cells = <0>;
57 };
58
59 spi_clk: dummy208m {
60 compatible = "fixed-clock";
61 clock-frequency = <208000000>;
62 #clock-cells = <0>;
63 };
64
65 hwver: hwver {
66 compatible = "mediatek,hwver", "syscon";
67 reg = <0 0x8000000 0 0x1000>;
68 };
69
70 timer {
71 compatible = "arm,armv8-timer";
72 interrupt-parent = <&gic>;
73 clock-frequency = <13000000>;
74 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
75 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
76 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
77 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
78 };
79
80 watchdog: watchdog@1001c000 {
81 compatible = "mediatek,mt7622-wdt",
82 "mediatek,mt6589-wdt",
83 "syscon";
84 reg = <0 0x1001c000 0 0x1000>;
85 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
86 #reset-cells = <1>;
87 };
88
89 gic: interrupt-controller@c000000 {
90 compatible = "arm,gic-v3";
91 #interrupt-cells = <3>;
92 interrupt-parent = <&gic>;
93 interrupt-controller;
94 reg = <0 0x0c000000 0 0x40000>, /* GICD */
95 <0 0x0c080000 0 0x200000>; /* GICR */
96 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
97 };
98
99 infracfg_ao_cgs: infracfg_ao_cgs@10001000 {
100 compatible = "mediatek,mt7988-infracfg_ao_cgs", "syscon";
101 reg = <0 0x10001000 0 0x1000>;
102 clock-parent = <&infracfg_ao>;
103 #clock-cells = <1>;
104 };
105
106 apmixedsys: apmixedsys@1001e000 {
107 compatible = "mediatek,mt7988-fixed-plls", "syscon";
108 reg = <0 0x1001e000 0 0x1000>;
109 #clock-cells = <1>;
110 };
111
112 topckgen: topckgen@1001b000 {
113 compatible = "mediatek,mt7988-topckgen", "syscon";
114 reg = <0 0x1001b000 0 0x1000>;
115 clock-parent = <&apmixedsys>;
116 #clock-cells = <1>;
117 };
118
119 pinctrl: pinctrl@1001f000 {
120 compatible = "mediatek,mt7988-pinctrl";
121 reg = <0 0x1001f000 0 0x1000>,
122 <0 0x11c10000 0 0x1000>,
123 <0 0x11d00000 0 0x1000>,
124 <0 0x11d20000 0 0x1000>,
125 <0 0x11e00000 0 0x1000>,
126 <0 0x11f00000 0 0x1000>,
127 <0 0x1000b000 0 0x1000>;
128 reg-names = "gpio_base", "iocfg_tr_base", "iocfg_br_base",
129 "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base",
130 "eint";
131 gpio: gpio-controller {
132 gpio-controller;
133 #gpio-cells = <2>;
134 };
135 };
136
137 sgmiisys0: syscon@10060000 {
138 compatible = "mediatek,mt7988-sgmiisys_0", "syscon";
139 reg = <0 0x10060000 0 0x1000>;
140 clock-parent = <&topckgen>;
141 #clock-cells = <1>;
142 };
143
144 sgmiisys1: syscon@10070000 {
145 compatible = "mediatek,mt7988-sgmiisys_1", "syscon";
146 reg = <0 0x10070000 0 0x1000>;
147 clock-parent = <&topckgen>;
148 #clock-cells = <1>;
149 };
150
151 usxgmiisys0: syscon@10080000 {
152 compatible = "mediatek,mt7988-usxgmiisys_0", "syscon";
153 reg = <0 0x10080000 0 0x1000>;
154 clock-parent = <&topckgen>;
155 #clock-cells = <1>;
156 };
157
158 usxgmiisys1: syscon@10081000 {
159 compatible = "mediatek,mt7988-usxgmiisys_1", "syscon";
160 reg = <0 0x10081000 0 0x1000>;
161 clock-parent = <&topckgen>;
162 #clock-cells = <1>;
163 };
164
Frank Wunderlich7950d172023-08-03 20:00:01 +0200[diff] [blame]165 dummy_clk: dummy12m {
166 compatible = "fixed-clock";
167 clock-frequency = <12000000>;
168 #clock-cells = <0>;
169 /* must need this line, or uart uanable to get dummy_clk */
170 bootph-all;
171 };
172
173 xhci1: xhci@11200000 {
174 compatible = "mediatek,mt7988-xhci",
175 "mediatek,mtk-xhci";
176 reg = <0 0x11200000 0 0x2e00>,
177 <0 0x11203e00 0 0x0100>;
178 reg-names = "mac", "ippc";
179 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
180 phys = <&tphyu2port0 PHY_TYPE_USB2>,
181 <&tphyu3port0 PHY_TYPE_USB3>;
182 clocks = <&dummy_clk>,
183 <&dummy_clk>,
184 <&dummy_clk>,
185 <&dummy_clk>,
186 <&dummy_clk>;
187 clock-names = "sys_ck",
188 "xhci_ck",
189 "ref_ck",
190 "mcu_ck",
191 "dma_ck";
192 #address-cells = <2>;
193 #size-cells = <2>;
194 status = "okay";
195 };
196
197 usbtphy: usb-phy@11c50000 {
198 compatible = "mediatek,mt7988",
199 "mediatek,generic-tphy-v2";
200 #address-cells = <2>;
201 #size-cells = <2>;
202 ranges;
203 status = "okay";
204
205 tphyu2port0: usb-phy@11c50000 {
206 reg = <0 0x11c50000 0 0x700>;
207 clocks = <&dummy_clk>;
208 clock-names = "ref";
209 #phy-cells = <1>;
210 status = "okay";
211 };
212
213 tphyu3port0: usb-phy@11c50700 {
214 reg = <0 0x11c50700 0 0x900>;
215 clocks = <&dummy_clk>;
216 clock-names = "ref";
217 #phy-cells = <1>;
218 mediatek,usb3-pll-ssc-delta;
219 mediatek,usb3-pll-ssc-delta1;
220 status = "okay";
221 };
222 };
223
developerf596c1a2023-07-19 17:17:49 +0800[diff] [blame]224 xfi_pextp0: syscon@11f20000 {
225 compatible = "mediatek,mt7988-xfi_pextp_0", "syscon";
226 reg = <0 0x11f20000 0 0x10000>;
227 clock-parent = <&topckgen>;
228 #clock-cells = <1>;
229 };
230
231 xfi_pextp1: syscon@11f30000 {
232 compatible = "mediatek,mt7988-xfi_pextp_1", "syscon";
233 reg = <0 0x11f30000 0 0x10000>;
234 clock-parent = <&topckgen>;
235 #clock-cells = <1>;
236 };
237
238 xfi_pll: syscon@11f40000 {
239 compatible = "mediatek,mt7988-xfi_pll", "syscon";
240 reg = <0 0x11f40000 0 0x1000>;
241 clock-parent = <&topckgen>;
242 #clock-cells = <1>;
243 };
244
245 topmisc: topmisc@11d10000 {
246 compatible = "mediatek,mt7988-topmisc", "syscon",
247 "mediatek,mt7988-power-controller";
248 reg = <0 0x11d10000 0 0x10000>;
249 clock-parent = <&topckgen>;
250 #clock-cells = <1>;
251 };
252
253 infracfg_ao: infracfg@10001000 {
254 compatible = "mediatek,mt7988-infracfg", "syscon";
255 reg = <0 0x10001000 0 0x1000>;
256 clock-parent = <&topckgen>;
257 #clock-cells = <1>;
258 };
259
260 uart0: serial@11000000 {
261 compatible = "mediatek,hsuart";
262 reg = <0 0x11000000 0 0x100>;
263 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART0_CK>;
265 assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
266 <&infracfg_ao CK_INFRA_MUX_UART0_SEL>;
267 assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
268 <&infracfg_ao CK_INFRA_UART_O0>;
269 status = "disabled";
270 };
271
272 uart1: serial@11000100 {
273 compatible = "mediatek,hsuart";
274 reg = <0 0x11000100 0 0x100>;
275 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART1_CK>;
277 assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
278 <&infracfg_ao CK_INFRA_MUX_UART1_SEL>;
279 assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
280 <&infracfg_ao CK_INFRA_UART_O1>;
281 status = "disabled";
282 };
283
284 uart2: serial@11000200 {
285 compatible = "mediatek,hsuart";
286 reg = <0 0x11000200 0 0x100>;
287 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART2_CK>;
289 assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
290 <&infracfg_ao CK_INFRA_MUX_UART2_SEL>;
291 assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
292 <&infracfg_ao CK_INFRA_UART_O2>;
293 status = "disabled";
294 };
295
296 i2c0: i2c@11003000 {
297 compatible = "mediatek,mt7988-i2c",
298 "mediatek,mt7981-i2c";
299 reg = <0 0x11003000 0 0x1000>,
300 <0 0x10217080 0 0x80>;
301 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
302 clock-div = <1>;
303 clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
304 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
305 clock-names = "main", "dma";
306 #address-cells = <1>;
307 #size-cells = <0>;
308 status = "disabled";
309 };
310
311 i2c1: i2c@11004000 {
312 compatible = "mediatek,mt7988-i2c",
313 "mediatek,mt7981-i2c";
314 reg = <0 0x11004000 0 0x1000>,
315 <0 0x10217100 0 0x80>;
316 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
317 clock-div = <1>;
318 clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
319 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
320 clock-names = "main", "dma";
321 #address-cells = <1>;
322 #size-cells = <0>;
323 status = "disabled";
324 };
325
326 i2c2: i2c@11005000 {
327 compatible = "mediatek,mt7988-i2c",
328 "mediatek,mt7981-i2c";
329 reg = <0 0x11005000 0 0x1000>,
330 <0 0x10217180 0 0x80>;
331 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
332 clock-div = <1>;
333 clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
334 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
335 clock-names = "main", "dma";
336 #address-cells = <1>;
337 #size-cells = <0>;
338 status = "disabled";
339 };
340
341 pwm: pwm@10048000 {
342 compatible = "mediatek,mt7988-pwm";
343 reg = <0 0x10048000 0 0x1000>;
344 #pwm-cells = <2>;
345 clocks = <&infracfg_ao CK_INFRA_66M_PWM_BCK>,
346 <&infracfg_ao CK_INFRA_66M_PWM_HCK>,
347 <&infracfg_ao CK_INFRA_66M_PWM_CK1>,
348 <&infracfg_ao CK_INFRA_66M_PWM_CK2>,
349 <&infracfg_ao CK_INFRA_66M_PWM_CK3>,
350 <&infracfg_ao CK_INFRA_66M_PWM_CK4>,
351 <&infracfg_ao CK_INFRA_66M_PWM_CK5>,
352 <&infracfg_ao CK_INFRA_66M_PWM_CK6>,
353 <&infracfg_ao CK_INFRA_66M_PWM_CK7>,
354 <&infracfg_ao CK_INFRA_66M_PWM_CK8>;
355 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
356 "pwm4","pwm5","pwm6","pwm7","pwm8";
357 status = "disabled";
358 };
359
360 snand: snand@11001000 {
361 compatible = "mediatek,mt7988-snand",
362 "mediatek,mt7986-snand";
363 reg = <0 0x11001000 0 0x1000>,
364 <0 0x11002000 0 0x1000>;
365 reg-names = "nfi", "ecc";
366 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&infracfg_ao CK_INFRA_SPINFI>,
368 <&infracfg_ao CK_INFRA_NFI>,
369 <&infracfg_ao CK_INFRA_66M_NFI_HCK>;
370 clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
371 assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
372 <&topckgen CK_TOP_NFI1X_SEL>;
373 assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
374 <&topckgen CK_TOP_CB_M_D8>;
375 status = "disabled";
376 };
377
378 spi0: spi@1100a000 {
379 compatible = "mediatek,ipm-spi";
380 reg = <0 0x11007000 0 0x100>;
381 clocks = <&spi_clk>,
382 <&spi_clk>;
383 clock-names = "sel-clk", "spi-clk";
384 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
385 status = "disabled";
386 };
387
388 spi1: spi@1100b000 {
389 compatible = "mediatek,ipm-spi";
390 reg = <0 0x11008000 0 0x100>;
391 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
392 status = "disabled";
393 };
394
395 spi2: spi@11009000 {
396 compatible = "mediatek,ipm-spi";
397 reg = <0 0x11009000 0 0x100>;
398 clocks = <&spi_clk>,
399 <&spi_clk>;
400 clock-names = "sel-clk", "spi-clk";
401 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
402 status = "disabled";
403 };
404
405 mmc0: mmc@11230000 {
406 compatible = "mediatek,mt7988-mmc",
407 "mediatek,mt7986-mmc";
408 reg = <0 0x11230000 0 0x1000>;
409 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&infracfg_ao_cgs CK_INFRA_MSDC400>,
411 <&infracfg_ao_cgs CK_INFRA_MSDC2_HCK>,
412 <&infracfg_ao_cgs CK_INFRA_133M_MSDC_0_HCK>,
413 <&infracfg_ao_cgs CK_INFRA_66M_MSDC_0_HCK>;
414 clock-names = "source", "hclk", "source_cg", "axi_cg";
415 status = "disabled";
416 };
417
418 ethdma: syscon@15000000 {
419 compatible = "mediatek,mt7988-ethdma", "syscon";
420 reg = <0 0x15000000 0 0x20000>;
421 clock-parent = <&topckgen>;
422 #clock-cells = <1>;
423 #reset-cells = <1>;
424 };
425
426 ethwarp: syscon@15031000 {
427 compatible = "mediatek,mt7988-ethwarp", "syscon";
428 reg = <0 0x15031000 0 0x1000>;
429 clock-parent = <&topckgen>;
430 #clock-cells = <1>;
431 #reset-cells = <1>;
432 };
433
434 eth: ethernet@15100000 {
435 compatible = "mediatek,mt7988-eth", "syscon";
436 reg = <0 0x15100000 0 0x20000>;
437 mediatek,ethsys = <&ethdma>;
438 mediatek,sgmiisys = <&sgmiisys0>;
439 mediatek,usxgmiisys = <&usxgmiisys0>;
440 mediatek,xfi_pextp = <&xfi_pextp0>;
441 mediatek,xfi_pll = <&xfi_pll>;
442 mediatek,infracfg = <&topmisc>;
443 mediatek,toprgu = <&watchdog>;
444 resets = <&ethdma ETHDMA_FE_RST>, <&ethwarp ETHWARP_GSW_RST>;
445 reset-names = "fe", "mcm";
446 #address-cells = <1>;
447 #size-cells = <0>;
448 mediatek,mcm;
449 status = "disabled";
450 };
451};