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git01.mediatek.com / filogic / uboot / c008690087698ef6713e6c92d0e68d8896043094 / . / arch / arm / dts / fsl-lx2160a-qds.dtsi
blob: e96605b1b4fb5e0e8bd16bcbb16afd54be1e0886 [file] [log] [blame]
Ioana Ciornei606f1402020-04-27 15:21:14 +0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * NXP LX2160AQDS common device tree source
4 *
Ioana Ciorneic0080632023-03-15 13:04:16 +0200[diff] [blame]5 * Copyright 2018-2020, 2023 NXP
Ioana Ciornei606f1402020-04-27 15:21:14 +0300[diff] [blame]6 *
7 */
8
9#include "fsl-lx2160a.dtsi"
10
Meenakshi Aggarwal8a03b0d2020-12-04 20:17:28 +0530[diff] [blame]11/ {
12 aliases {
13 spi0 = &fspi;
Ioana Ciorneic0080632023-03-15 13:04:16 +0200[diff] [blame]14 serial0 = &uart0;
Meenakshi Aggarwal8a03b0d2020-12-04 20:17:28 +0530[diff] [blame]15 };
16};
17
Ioana Ciornei606f1402020-04-27 15:21:14 +0300[diff] [blame]18&dpmac17 {
19 status = "okay";
20 phy-handle = <&rgmii_phy1>;
21 phy-connection-type = "rgmii-id";
22};
23
24&dpmac18 {
25 status = "okay";
26 phy-handle = <&rgmii_phy2>;
27 phy-connection-type = "rgmii-id";
28};
29
Zhao Qiangaa73e402020-06-08 11:28:24 +0800[diff] [blame]30&dspi0 {
31 bus-num = <0>;
32 status = "okay";
33
34 dflash0: n25q128a {
35 #address-cells = <1>;
36 #size-cells = <1>;
37 compatible = "spi-flash";
38 spi-max-frequency = <3000000>;
39 spi-cpol;
40 spi-cpha;
41 reg = <0>;
42 };
43 dflash1: sst25wf040b {
44 #address-cells = <1>;
45 #size-cells = <1>;
46 compatible = "spi-flash";
47 spi-max-frequency = <3000000>;
48 spi-cpol;
49 spi-cpha;
50 reg = <1>;
51 };
52 dflash2: en25s64 {
53 #address-cells = <1>;
54 #size-cells = <1>;
55 compatible = "spi-flash";
56 spi-max-frequency = <3000000>;
57 spi-cpol;
58 spi-cpha;
59 reg = <2>;
60 };
61};
62
63&dspi1 {
64 bus-num = <0>;
65 status = "okay";
66
67 dflash3: n25q128a {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "spi-flash";
71 spi-max-frequency = <3000000>;
72 spi-cpol;
73 spi-cpha;
74 reg = <0>;
75 };
76 dflash4: sst25wf040b {
77 #address-cells = <1>;
78 #size-cells = <1>;
79 compatible = "spi-flash";
80 spi-max-frequency = <3000000>;
81 spi-cpol;
82 spi-cpha;
83 reg = <1>;
84 };
85 dflash5: en25s64 {
86 #address-cells = <1>;
87 #size-cells = <1>;
88 compatible = "spi-flash";
89 spi-max-frequency = <3000000>;
90 spi-cpol;
91 spi-cpha;
92 reg = <2>;
93 };
94};
95
96&dspi2 {
97 bus-num = <0>;
98 status = "okay";
99
100 dflash6: n25q128a {
101 #address-cells = <1>;
102 #size-cells = <1>;
103 compatible = "spi-flash";
104 spi-max-frequency = <3000000>;
105 spi-cpol;
106 spi-cpha;
107 reg = <0>;
108 };
109 dflash7: sst25wf040b {
110 #address-cells = <1>;
111 #size-cells = <1>;
112 compatible = "spi-flash";
113 spi-max-frequency = <3000000>;
114 spi-cpol;
115 spi-cpha;
116 reg = <1>;
117 };
118 dflash8: en25s64 {
119 #address-cells = <1>;
120 #size-cells = <1>;
121 compatible = "spi-flash";
122 spi-max-frequency = <3000000>;
123 spi-cpol;
124 spi-cpha;
125 reg = <2>;
126 };
127};
128
Ioana Ciornei606f1402020-04-27 15:21:14 +0300[diff] [blame]129&emdio1 {
130 status = "okay";
131};
132
133&emdio2 {
134 status = "okay";
135};
136
137&esdhc0 {
138 status = "okay";
139};
140
141&esdhc1 {
142 status = "okay";
143};
144
145&i2c0 {
146 status = "okay";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]147 bootph-all;
Ioana Ciornei606f1402020-04-27 15:21:14 +0300[diff] [blame]148
149 fpga@66 {
150 #address-cells = <1>;
151 #size-cells = <0>;
152 compatible = "simple-mfd";
153 reg = <0x66>;
154
155 mux-mdio@54 {
156 #address-cells = <1>;
157 #size-cells = <0>;
158 compatible = "mdio-mux-i2creg";
159 reg = <0x54>;
160 #mux-control-cells = <1>;
161 mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3
162 mdio-parent-bus = <&emdio1>;
163
164 mdio@00 {
165 #address-cells = <1>;
166 #size-cells = <0>;
167 reg = <0x00>;
168
169 rgmii_phy1: ethernet-phy@1 {
170 reg = <0x1>;
171 };
172 };
173 mdio@08 {
174 #address-cells = <1>;
175 #size-cells = <0>;
176 reg = <0x40>;
177
178 rgmii_phy2: ethernet-phy@2 {
179 reg = <0x2>;
180 };
181 };
182
183 emdio1_slot1: mdio@c0 { /* I/O Slot #1 */
184 reg = <0xC0>;
185 device-name = "emdio1_slot1";
186 #address-cells = <1>;
187 #size-cells = <0>;
188 };
189
190 emdio1_slot2: mdio@c8 { /* I/O Slot #2 */
191 reg = <0xC8>;
192 device-name = "emdio1_slot2";
193 #address-cells = <1>;
194 #size-cells = <0>;
195 };
196
197 emdio1_slot3: mdio@d0 { /* I/O Slot #3 */
198 reg = <0xD0>;
199 device-name = "emdio1_slot3";
200 #address-cells = <1>;
201 #size-cells = <0>;
202 };
203
204 emdio1_slot4: mdio@d8 { /* I/O Slot #4 */
205 reg = <0xD8>;
206 device-name = "emdio1_slot4";
207 #address-cells = <1>;
208 #size-cells = <0>;
209 };
210
211 emdio1_slot5: mdio@e0 { /* I/O Slot #5 */
212 reg = <0xE0>;
213 device-name = "emdio1_slot5";
214 #address-cells = <1>;
215 #size-cells = <0>;
216 };
217
218 emdio1_slot6: mdio@e8 { /* I/O Slot #6 */
219 reg = <0xE8>;
220 device-name = "emdio1_slot6";
221 #address-cells = <1>;
222 #size-cells = <0>;
223 };
224
225 emdio1_slot7: mdio@f0 { /* I/O Slot #7 */
226 reg = <0xF0>;
227 device-name = "emdio1_slot7";
228 #address-cells = <1>;
229 #size-cells = <0>;
230 };
231
232 emdio1_slot8: mdio@f8 { /* I/O Slot #8 */
233 reg = <0xF8>;
234 device-name = "emdio1_slot8";
235 #address-cells = <1>;
236 #size-cells = <0>;
237 };
238 };
239
240 };
241
242 i2c-mux@77 {
243 compatible = "nxp,pca9547";
244 reg = <0x77>;
245 #address-cells = <1>;
246 #size-cells = <0>;
247
248 i2c@3 {
249 #address-cells = <1>;
250 #size-cells = <0>;
251 reg = <0x3>;
252
253 rtc@51 {
Vladimir Olteanebda2782022-01-03 14:47:26 +0200[diff] [blame]254 compatible = "nxp,pcf2129";
Ioana Ciornei606f1402020-04-27 15:21:14 +0300[diff] [blame]255 reg = <0x51>;
256 };
257 };
258 };
259};
260
Meenakshi Aggarwal8a03b0d2020-12-04 20:17:28 +0530[diff] [blame]261&fspi {
262 status = "okay";
263
264 mt35xu512aba0: flash@0 {
265 #address-cells = <1>;
266 #size-cells = <1>;
267 compatible = "jedec,spi-nor";
268 spi-max-frequency = <50000000>;
269 reg = <0>;
270 spi-rx-bus-width = <8>;
271 spi-tx-bus-width = <1>;
272 };
273};
274
Ioana Ciornei606f1402020-04-27 15:21:14 +0300[diff] [blame]275&sata0 {
276 status = "okay";
277};
278
279&sata1 {
280 status = "okay";
281};
282
283&sata2 {
284 status = "okay";
285};
286
287&sata3 {
288 status = "okay";
289};
Ioana Ciorneic0080632023-03-15 13:04:16 +0200[diff] [blame]290
291&uart0 {
292 status = "okay";
293};
294
295&uart1 {
296 status = "okay";
297};