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git01.mediatek.com / filogic / uboot / c008690087698ef6713e6c92d0e68d8896043094 / . / arch / arm / dts / dra74x.dtsi
blob: 9ade216cd457b21a72fd17ab13a3fbcbb15cc951 [file] [log] [blame]
Andrew Davis05618992023-04-11 13:24:58 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-only
Mugunthan V N0f148312015-09-22 18:45:12 +0530[diff] [blame]2/*
Andrew Davis05618992023-04-11 13:24:58 -0500[diff] [blame]3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
Mugunthan V N0f148312015-09-22 18:45:12 +0530[diff] [blame]4 *
Mugunthan V N0f148312015-09-22 18:45:12 +0530[diff] [blame]5 * Based on "omap4.dtsi"
6 */
7
8#include "dra7.dtsi"
9
10/ {
11 compatible = "ti,dra742", "ti,dra74", "ti,dra7";
12
13 cpus {
Mugunthan V N0f148312015-09-22 18:45:12 +0530[diff] [blame]14 cpu@1 {
15 device_type = "cpu";
16 compatible = "arm,cortex-a15";
17 reg = <1>;
Lokesh Vutlacfa23a42017-08-21 12:50:59 +0530[diff] [blame]18 operating-points-v2 = <&cpu0_opp_table>;
Mugunthan V N0f148312015-09-22 18:45:12 +0530[diff] [blame]19 };
20 };
21
22 pmu {
23 compatible = "arm,cortex-a15-pmu";
24 interrupt-parent = <&wakeupgen>;
25 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
26 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
27 };
28
29 ocp {
Lokesh Vutlacfa23a42017-08-21 12:50:59 +0530[diff] [blame]30 dsp2_system: dsp_system@41500000 {
31 compatible = "syscon";
32 reg = <0x41500000 0x100>;
33 };
34
Mugunthan V N0f148312015-09-22 18:45:12 +0530[diff] [blame]35 omap_dwc3_4: omap_dwc3_4@48940000 {
36 compatible = "ti,dwc3";
37 ti,hwmods = "usb_otg_ss4";
38 reg = <0x48940000 0x10000>;
39 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
40 #address-cells = <1>;
41 #size-cells = <1>;
42 utmi-mode = <2>;
43 ranges;
44 status = "disabled";
45 usb4: usb@48950000 {
46 compatible = "snps,dwc3";
47 reg = <0x48950000 0x17000>;
Lokesh Vutlacfa23a42017-08-21 12:50:59 +0530[diff] [blame]48 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
49 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
50 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
51 interrupt-names = "peripheral",
52 "host",
53 "otg";
Mugunthan V N0f148312015-09-22 18:45:12 +0530[diff] [blame]54 maximum-speed = "high-speed";
55 dr_mode = "otg";
56 };
57 };
Lokesh Vutlacfa23a42017-08-21 12:50:59 +0530[diff] [blame]58
59 mmu0_dsp2: mmu@41501000 {
60 compatible = "ti,dra7-dsp-iommu";
61 reg = <0x41501000 0x100>;
62 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
63 ti,hwmods = "mmu0_dsp2";
64 #iommu-cells = <0>;
65 ti,syscon-mmuconfig = <&dsp2_system 0x0>;
66 status = "disabled";
67 };
68
69 mmu1_dsp2: mmu@41502000 {
70 compatible = "ti,dra7-dsp-iommu";
71 reg = <0x41502000 0x100>;
72 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
73 ti,hwmods = "mmu1_dsp2";
74 #iommu-cells = <0>;
75 ti,syscon-mmuconfig = <&dsp2_system 0x1>;
76 status = "disabled";
77 };
Mugunthan V N0f148312015-09-22 18:45:12 +0530[diff] [blame]78 };
79};
80
Lokesh Vutlacfa23a42017-08-21 12:50:59 +0530[diff] [blame]81&cpu0_opp_table {
82 opp-shared;
83};
84
Mugunthan V N0f148312015-09-22 18:45:12 +0530[diff] [blame]85&dss {
86 reg = <0x58000000 0x80>,
87 <0x58004054 0x4>,
88 <0x58004300 0x20>,
Lokesh Vutlacfa23a42017-08-21 12:50:59 +0530[diff] [blame]89 <0x58009054 0x4>,
90 <0x58009300 0x20>;
Mugunthan V N0f148312015-09-22 18:45:12 +0530[diff] [blame]91 reg-names = "dss", "pll1_clkctrl", "pll1",
92 "pll2_clkctrl", "pll2";
93
94 clocks = <&dss_dss_clk>,
95 <&dss_video1_clk>,
96 <&dss_video2_clk>;
97 clock-names = "fck", "video1_clk", "video2_clk";
98};
Lokesh Vutlacfa23a42017-08-21 12:50:59 +0530[diff] [blame]99
100&mailbox5 {
Andrew Davis0429d3f2023-04-11 13:25:06 -0500[diff] [blame]101 mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
Lokesh Vutlacfa23a42017-08-21 12:50:59 +0530[diff] [blame]102 ti,mbox-tx = <6 2 2>;
103 ti,mbox-rx = <4 2 2>;
104 status = "disabled";
105 };
Andrew Davis0429d3f2023-04-11 13:25:06 -0500[diff] [blame]106 mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
Lokesh Vutlacfa23a42017-08-21 12:50:59 +0530[diff] [blame]107 ti,mbox-tx = <5 2 2>;
108 ti,mbox-rx = <1 2 2>;
109 status = "disabled";
110 };
111};
112
113&mailbox6 {
Andrew Davis0429d3f2023-04-11 13:25:06 -0500[diff] [blame]114 mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
Lokesh Vutlacfa23a42017-08-21 12:50:59 +0530[diff] [blame]115 ti,mbox-tx = <6 2 2>;
116 ti,mbox-rx = <4 2 2>;
117 status = "disabled";
118 };
Andrew Davis0429d3f2023-04-11 13:25:06 -0500[diff] [blame]119 mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
Lokesh Vutlacfa23a42017-08-21 12:50:59 +0530[diff] [blame]120 ti,mbox-tx = <5 2 2>;
121 ti,mbox-rx = <1 2 2>;
122 status = "disabled";
123 };
124};