| William Zhang | 26b895d | 2022-08-05 18:34:03 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later OR MIT |
| 2 | |
| 3 | #include <dt-bindings/interrupt-controller/irq.h> |
| 4 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 5 | |
| 6 | /dts-v1/; |
| 7 | |
| 8 | / { |
| 9 | compatible = "brcm,bcm4908", "brcm,bcmbca"; |
| 10 | |
| 11 | interrupt-parent = <&gic>; |
| 12 | |
| 13 | #address-cells = <2>; |
| 14 | #size-cells = <2>; |
| 15 | |
| 16 | aliases { |
| 17 | serial0 = &uart0; |
| 18 | }; |
| 19 | |
| 20 | chosen { |
| 21 | stdout-path = "serial0:115200n8"; |
| 22 | }; |
| 23 | |
| 24 | cpus { |
| 25 | #address-cells = <1>; |
| 26 | #size-cells = <0>; |
| 27 | |
| 28 | cpu0: cpu@0 { |
| 29 | device_type = "cpu"; |
| 30 | compatible = "brcm,brahma-b53"; |
| 31 | reg = <0x0>; |
| 32 | enable-method = "spin-table"; |
| 33 | cpu-release-addr = <0x0 0xfff8>; |
| 34 | next-level-cache = <&l2>; |
| 35 | }; |
| 36 | |
| 37 | cpu1: cpu@1 { |
| 38 | device_type = "cpu"; |
| 39 | compatible = "brcm,brahma-b53"; |
| 40 | reg = <0x1>; |
| 41 | enable-method = "spin-table"; |
| 42 | cpu-release-addr = <0x0 0xfff8>; |
| 43 | next-level-cache = <&l2>; |
| 44 | }; |
| 45 | |
| 46 | cpu2: cpu@2 { |
| 47 | device_type = "cpu"; |
| 48 | compatible = "brcm,brahma-b53"; |
| 49 | reg = <0x2>; |
| 50 | enable-method = "spin-table"; |
| 51 | cpu-release-addr = <0x0 0xfff8>; |
| 52 | next-level-cache = <&l2>; |
| 53 | }; |
| 54 | |
| 55 | cpu3: cpu@3 { |
| 56 | device_type = "cpu"; |
| 57 | compatible = "brcm,brahma-b53"; |
| 58 | reg = <0x3>; |
| 59 | enable-method = "spin-table"; |
| 60 | cpu-release-addr = <0x0 0xfff8>; |
| 61 | next-level-cache = <&l2>; |
| 62 | }; |
| 63 | |
| 64 | l2: l2-cache0 { |
| 65 | compatible = "cache"; |
| 66 | }; |
| 67 | }; |
| 68 | |
| 69 | axi@81000000 { |
| 70 | compatible = "simple-bus"; |
| 71 | #address-cells = <1>; |
| 72 | #size-cells = <1>; |
| 73 | ranges = <0x00 0x00 0x81000000 0x4000>; |
| 74 | |
| 75 | gic: interrupt-controller@1000 { |
| 76 | compatible = "arm,gic-400"; |
| 77 | #interrupt-cells = <3>; |
| 78 | #address-cells = <0>; |
| 79 | interrupt-controller; |
| 80 | reg = <0x1000 0x1000>, |
| 81 | <0x2000 0x2000>; |
| 82 | }; |
| 83 | }; |
| 84 | |
| 85 | timer { |
| 86 | compatible = "arm,armv8-timer"; |
| 87 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 88 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 89 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 90 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| 91 | }; |
| 92 | |
| 93 | pmu { |
| 94 | compatible = "arm,cortex-a53-pmu"; |
| 95 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| 96 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, |
| 97 | <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, |
| 98 | <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| 99 | interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; |
| 100 | }; |
| 101 | |
| 102 | clocks { |
| 103 | periph_clk: periph_clk { |
| 104 | compatible = "fixed-clock"; |
| 105 | #clock-cells = <0>; |
| 106 | clock-frequency = <50000000>; |
| 107 | clock-output-names = "periph"; |
| 108 | }; |
| 109 | }; |
| 110 | |
| 111 | bus@ff800000 { |
| 112 | compatible = "simple-bus"; |
| 113 | #address-cells = <1>; |
| 114 | #size-cells = <1>; |
| 115 | ranges = <0x00 0x00 0xff800000 0x3000>; |
| 116 | |
| 117 | uart0: serial@640 { |
| 118 | compatible = "brcm,bcm6345-uart"; |
| 119 | reg = <0x640 0x18>; |
| 120 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| 121 | clocks = <&periph_clk>; |
| 122 | clock-names = "refclk"; |
| 123 | status = "disabled"; |
| 124 | }; |
| 125 | |
| 126 | }; |
| 127 | }; |