wdenk | 717b5aa | 2002-04-27 11:09:31 +0000 | [diff] [blame] | 1 | /* |
| 2 | * NS16550 Serial Port |
Stefan Roese | 88fbf93 | 2010-04-15 16:07:28 +0200 | [diff] [blame] | 3 | * originally from linux source (arch/powerpc/boot/ns16550.h) |
Detlev Zundel | 166fb54 | 2009-04-03 11:53:01 +0200 | [diff] [blame] | 4 | * |
| 5 | * Cleanup and unification |
| 6 | * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH |
| 7 | * |
wdenk | 717b5aa | 2002-04-27 11:09:31 +0000 | [diff] [blame] | 8 | * modified slightly to |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 9 | * have addresses as offsets from CONFIG_SYS_ISA_BASE |
wdenk | 717b5aa | 2002-04-27 11:09:31 +0000 | [diff] [blame] | 10 | * added a few more definitions |
| 11 | * added prototypes for ns16550.c |
| 12 | * reduced no of com ports to 2 |
| 13 | * modifications (c) Rob Taylor, Flying Pig Systems. 2000. |
Wolfgang Denk | ba94093 | 2006-07-19 13:50:38 +0200 | [diff] [blame] | 14 | * |
Heiko Schocher | d7f77fb | 2006-06-19 11:02:41 +0200 | [diff] [blame] | 15 | * added support for port on 64-bit bus |
| 16 | * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems |
wdenk | 717b5aa | 2002-04-27 11:09:31 +0000 | [diff] [blame] | 17 | */ |
| 18 | |
Detlev Zundel | 937ca56 | 2009-04-03 16:45:46 +0200 | [diff] [blame] | 19 | /* |
| 20 | * Note that the following macro magic uses the fact that the compiler |
| 21 | * will not allocate storage for arrays of size 0 |
| 22 | */ |
| 23 | |
Dave Aldridge | a51bebc | 2011-09-01 22:47:14 +0000 | [diff] [blame] | 24 | #include <linux/types.h> |
| 25 | |
Simon Glass | 79a9da3 | 2014-09-04 16:27:34 -0600 | [diff] [blame] | 26 | #ifdef CONFIG_DM_SERIAL |
| 27 | /* |
| 28 | * For driver model we always use one byte per register, and sort out the |
| 29 | * differences in the driver |
| 30 | */ |
| 31 | #define CONFIG_SYS_NS16550_REG_SIZE (-1) |
| 32 | #endif |
| 33 | |
Detlev Zundel | 937ca56 | 2009-04-03 16:45:46 +0200 | [diff] [blame] | 34 | #if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0) |
wdenk | 717b5aa | 2002-04-27 11:09:31 +0000 | [diff] [blame] | 35 | #error "Please define NS16550 registers size." |
Simon Glass | 0b31ec7 | 2015-05-12 14:55:02 -0600 | [diff] [blame] | 36 | #elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_DM_SERIAL) |
Dave Aldridge | a51bebc | 2011-09-01 22:47:14 +0000 | [diff] [blame] | 37 | #define UART_REG(x) u32 x |
Detlev Zundel | 937ca56 | 2009-04-03 16:45:46 +0200 | [diff] [blame] | 38 | #elif (CONFIG_SYS_NS16550_REG_SIZE > 0) |
| 39 | #define UART_REG(x) \ |
| 40 | unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \ |
| 41 | unsigned char x; |
| 42 | #elif (CONFIG_SYS_NS16550_REG_SIZE < 0) |
| 43 | #define UART_REG(x) \ |
| 44 | unsigned char x; \ |
| 45 | unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1]; |
wdenk | 717b5aa | 2002-04-27 11:09:31 +0000 | [diff] [blame] | 46 | #endif |
| 47 | |
Simon Glass | 79a9da3 | 2014-09-04 16:27:34 -0600 | [diff] [blame] | 48 | /** |
| 49 | * struct ns16550_platdata - information about a NS16550 port |
| 50 | * |
| 51 | * @base: Base register address |
| 52 | * @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...) |
| 53 | * @clock: UART base clock speed in Hz |
| 54 | */ |
| 55 | struct ns16550_platdata { |
Simon Glass | 2546394 | 2014-10-22 21:37:04 -0600 | [diff] [blame] | 56 | unsigned long base; |
Simon Glass | 79a9da3 | 2014-09-04 16:27:34 -0600 | [diff] [blame] | 57 | int reg_shift; |
| 58 | int clock; |
Michal Simek | 7e0cdc4 | 2016-02-16 16:17:49 +0100 | [diff] [blame] | 59 | int reg_offset; |
Marek Vasut | f523c9c | 2016-12-01 02:06:29 +0100 | [diff] [blame] | 60 | u32 fcr; |
Simon Glass | 79a9da3 | 2014-09-04 16:27:34 -0600 | [diff] [blame] | 61 | }; |
| 62 | |
| 63 | struct udevice; |
| 64 | |
Detlev Zundel | 937ca56 | 2009-04-03 16:45:46 +0200 | [diff] [blame] | 65 | struct NS16550 { |
| 66 | UART_REG(rbr); /* 0 */ |
| 67 | UART_REG(ier); /* 1 */ |
| 68 | UART_REG(fcr); /* 2 */ |
| 69 | UART_REG(lcr); /* 3 */ |
| 70 | UART_REG(mcr); /* 4 */ |
| 71 | UART_REG(lsr); /* 5 */ |
| 72 | UART_REG(msr); /* 6 */ |
| 73 | UART_REG(spr); /* 7 */ |
Mikhail Kshevetskiy | f9da3a3 | 2012-07-09 08:52:43 +0000 | [diff] [blame] | 74 | #ifdef CONFIG_SOC_DA8XX |
| 75 | UART_REG(reg8); /* 8 */ |
| 76 | UART_REG(reg9); /* 9 */ |
| 77 | UART_REG(revid1); /* A */ |
| 78 | UART_REG(revid2); /* B */ |
| 79 | UART_REG(pwr_mgmt); /* C */ |
| 80 | UART_REG(mdr1); /* D */ |
| 81 | #else |
Detlev Zundel | 937ca56 | 2009-04-03 16:45:46 +0200 | [diff] [blame] | 82 | UART_REG(mdr1); /* 8 */ |
| 83 | UART_REG(reg9); /* 9 */ |
| 84 | UART_REG(regA); /* A */ |
| 85 | UART_REG(regB); /* B */ |
| 86 | UART_REG(regC); /* C */ |
| 87 | UART_REG(regD); /* D */ |
| 88 | UART_REG(regE); /* E */ |
| 89 | UART_REG(uasr); /* F */ |
| 90 | UART_REG(scr); /* 10*/ |
| 91 | UART_REG(ssr); /* 11*/ |
Mikhail Kshevetskiy | f9da3a3 | 2012-07-09 08:52:43 +0000 | [diff] [blame] | 92 | #endif |
Simon Glass | 79a9da3 | 2014-09-04 16:27:34 -0600 | [diff] [blame] | 93 | #ifdef CONFIG_DM_SERIAL |
| 94 | struct ns16550_platdata *plat; |
| 95 | #endif |
Detlev Zundel | 937ca56 | 2009-04-03 16:45:46 +0200 | [diff] [blame] | 96 | }; |
| 97 | |
wdenk | 717b5aa | 2002-04-27 11:09:31 +0000 | [diff] [blame] | 98 | #define thr rbr |
| 99 | #define iir fcr |
| 100 | #define dll rbr |
| 101 | #define dlm ier |
| 102 | |
Simon Glass | dd5497c | 2011-10-15 19:14:09 +0000 | [diff] [blame] | 103 | typedef struct NS16550 *NS16550_t; |
wdenk | 717b5aa | 2002-04-27 11:09:31 +0000 | [diff] [blame] | 104 | |
Detlev Zundel | 166fb54 | 2009-04-03 11:53:01 +0200 | [diff] [blame] | 105 | /* |
| 106 | * These are the definitions for the FIFO Control Register |
| 107 | */ |
Simon Glass | dd5497c | 2011-10-15 19:14:09 +0000 | [diff] [blame] | 108 | #define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ |
Detlev Zundel | 166fb54 | 2009-04-03 11:53:01 +0200 | [diff] [blame] | 109 | #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ |
| 110 | #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ |
| 111 | #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ |
| 112 | #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ |
| 113 | #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ |
| 114 | #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ |
| 115 | #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ |
| 116 | #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ |
| 117 | |
| 118 | #define UART_FCR_RXSR 0x02 /* Receiver soft reset */ |
| 119 | #define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ |
wdenk | 717b5aa | 2002-04-27 11:09:31 +0000 | [diff] [blame] | 120 | |
Marek Vasut | 92a744f | 2016-12-01 02:06:31 +0100 | [diff] [blame] | 121 | /* Ingenic JZ47xx specific UART-enable bit. */ |
| 122 | #define UART_FCR_UME 0x10 |
| 123 | |
Detlev Zundel | 166fb54 | 2009-04-03 11:53:01 +0200 | [diff] [blame] | 124 | /* |
| 125 | * These are the definitions for the Modem Control Register |
| 126 | */ |
| 127 | #define UART_MCR_DTR 0x01 /* DTR */ |
| 128 | #define UART_MCR_RTS 0x02 /* RTS */ |
| 129 | #define UART_MCR_OUT1 0x04 /* Out 1 */ |
| 130 | #define UART_MCR_OUT2 0x08 /* Out 2 */ |
| 131 | #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ |
Karicheri, Muralidharan | cbc0888 | 2014-04-09 15:38:46 -0400 | [diff] [blame] | 132 | #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */ |
Detlev Zundel | 166fb54 | 2009-04-03 11:53:01 +0200 | [diff] [blame] | 133 | |
| 134 | #define UART_MCR_DMA_EN 0x04 |
| 135 | #define UART_MCR_TX_DFR 0x08 |
wdenk | 717b5aa | 2002-04-27 11:09:31 +0000 | [diff] [blame] | 136 | |
Detlev Zundel | 166fb54 | 2009-04-03 11:53:01 +0200 | [diff] [blame] | 137 | /* |
| 138 | * These are the definitions for the Line Control Register |
| 139 | * |
| 140 | * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting |
| 141 | * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. |
| 142 | */ |
| 143 | #define UART_LCR_WLS_MSK 0x03 /* character length select mask */ |
| 144 | #define UART_LCR_WLS_5 0x00 /* 5 bit character length */ |
| 145 | #define UART_LCR_WLS_6 0x01 /* 6 bit character length */ |
| 146 | #define UART_LCR_WLS_7 0x02 /* 7 bit character length */ |
| 147 | #define UART_LCR_WLS_8 0x03 /* 8 bit character length */ |
Simon Glass | dd5497c | 2011-10-15 19:14:09 +0000 | [diff] [blame] | 148 | #define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */ |
Detlev Zundel | 166fb54 | 2009-04-03 11:53:01 +0200 | [diff] [blame] | 149 | #define UART_LCR_PEN 0x08 /* Parity eneble */ |
| 150 | #define UART_LCR_EPS 0x10 /* Even Parity Select */ |
| 151 | #define UART_LCR_STKP 0x20 /* Stick Parity */ |
| 152 | #define UART_LCR_SBRK 0x40 /* Set Break */ |
| 153 | #define UART_LCR_BKSE 0x80 /* Bank select enable */ |
| 154 | #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
wdenk | 717b5aa | 2002-04-27 11:09:31 +0000 | [diff] [blame] | 155 | |
Detlev Zundel | 166fb54 | 2009-04-03 11:53:01 +0200 | [diff] [blame] | 156 | /* |
| 157 | * These are the definitions for the Line Status Register |
| 158 | */ |
| 159 | #define UART_LSR_DR 0x01 /* Data ready */ |
| 160 | #define UART_LSR_OE 0x02 /* Overrun */ |
| 161 | #define UART_LSR_PE 0x04 /* Parity error */ |
| 162 | #define UART_LSR_FE 0x08 /* Framing error */ |
| 163 | #define UART_LSR_BI 0x10 /* Break */ |
| 164 | #define UART_LSR_THRE 0x20 /* Xmit holding register empty */ |
| 165 | #define UART_LSR_TEMT 0x40 /* Xmitter empty */ |
| 166 | #define UART_LSR_ERR 0x80 /* Error */ |
| 167 | |
| 168 | #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ |
| 169 | #define UART_MSR_RI 0x40 /* Ring Indicator */ |
| 170 | #define UART_MSR_DSR 0x20 /* Data Set Ready */ |
| 171 | #define UART_MSR_CTS 0x10 /* Clear to Send */ |
| 172 | #define UART_MSR_DDCD 0x08 /* Delta DCD */ |
| 173 | #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ |
| 174 | #define UART_MSR_DDSR 0x02 /* Delta DSR */ |
| 175 | #define UART_MSR_DCTS 0x01 /* Delta CTS */ |
| 176 | |
| 177 | /* |
| 178 | * These are the definitions for the Interrupt Identification Register |
| 179 | */ |
| 180 | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
| 181 | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ |
| 182 | |
| 183 | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ |
| 184 | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
| 185 | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
| 186 | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
| 187 | |
| 188 | /* |
| 189 | * These are the definitions for the Interrupt Enable Register |
| 190 | */ |
| 191 | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ |
| 192 | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
| 193 | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
| 194 | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ |
wdenk | 717b5aa | 2002-04-27 11:09:31 +0000 | [diff] [blame] | 195 | |
wdenk | 717b5aa | 2002-04-27 11:09:31 +0000 | [diff] [blame] | 196 | /* useful defaults for LCR */ |
Detlev Zundel | 166fb54 | 2009-04-03 11:53:01 +0200 | [diff] [blame] | 197 | #define UART_LCR_8N1 0x03 |
wdenk | 717b5aa | 2002-04-27 11:09:31 +0000 | [diff] [blame] | 198 | |
Simon Glass | dd5497c | 2011-10-15 19:14:09 +0000 | [diff] [blame] | 199 | void NS16550_init(NS16550_t com_port, int baud_divisor); |
| 200 | void NS16550_putc(NS16550_t com_port, char c); |
| 201 | char NS16550_getc(NS16550_t com_port); |
| 202 | int NS16550_tstc(NS16550_t com_port); |
| 203 | void NS16550_reinit(NS16550_t com_port, int baud_divisor); |
Simon Glass | e98e01e | 2014-09-04 16:27:32 -0600 | [diff] [blame] | 204 | |
| 205 | /** |
| 206 | * ns16550_calc_divisor() - calculate the divisor given clock and baud rate |
| 207 | * |
| 208 | * Given the UART input clock and required baudrate, calculate the divisor |
| 209 | * that should be used. |
| 210 | * |
| 211 | * @port: UART port |
| 212 | * @clock: UART input clock speed in Hz |
| 213 | * @baudrate: Required baud rate |
| 214 | * @return baud rate divisor that should be used |
| 215 | */ |
| 216 | int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate); |
Simon Glass | 79a9da3 | 2014-09-04 16:27:34 -0600 | [diff] [blame] | 217 | |
| 218 | /** |
| 219 | * ns16550_serial_ofdata_to_platdata() - convert DT to platform data |
| 220 | * |
| 221 | * Decode a device tree node for an ns16550 device. This includes the |
| 222 | * register base address and register shift properties. The caller must set |
| 223 | * up the clock frequency. |
| 224 | * |
| 225 | * @dev: dev to decode platform data for |
| 226 | * @return: 0 if OK, -EINVAL on error |
| 227 | */ |
| 228 | int ns16550_serial_ofdata_to_platdata(struct udevice *dev); |
| 229 | |
| 230 | /** |
| 231 | * ns16550_serial_probe() - probe a serial port |
| 232 | * |
| 233 | * This sets up the serial port ready for use, except for the baud rate |
| 234 | * @return 0, or -ve on error |
| 235 | */ |
| 236 | int ns16550_serial_probe(struct udevice *dev); |
| 237 | |
| 238 | /** |
| 239 | * struct ns16550_serial_ops - ns16550 serial operations |
| 240 | * |
| 241 | * These should be used by the client driver for the driver's 'ops' member |
| 242 | */ |
| 243 | extern const struct dm_serial_ops ns16550_serial_ops; |