Marek Vasut | 1f7ba64 | 2024-12-12 14:34:30 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2024 Renesas Electronics Corp. |
| 4 | */ |
| 5 | |
| 6 | #include <asm/io.h> |
| 7 | #include <dm.h> |
| 8 | #include <errno.h> |
| 9 | #include <ram.h> |
| 10 | #include <linux/sizes.h> |
| 11 | |
| 12 | /* RT-VRAM register base address */ |
| 13 | #define RTVRAM_VBUF_CFG 0x6504 |
| 14 | #define RTVRAM_VBUF_CFG_CACHE_MODE_8WAY (1 << 8) |
| 15 | #define RTVRAM_VBUF_CFG_VBUF_SIZE_28M (6 << 0) |
| 16 | #define RTVRAM_EXT_MODE 0x8500 |
| 17 | #define RTVRAM_EXT_MODE_EXT BIT(0) |
| 18 | #define RTVRAM_VBUF_BADDR 0xC580 |
| 19 | |
| 20 | #define RTVRAM_VBUF_NUM 7 |
| 21 | |
| 22 | #define SDRAM_40BIT_ADDR_TOP 0x0400000000ULL |
| 23 | #define RTVRAM_VBUF_AREA_SIZE SZ_4M |
| 24 | |
| 25 | struct renesas_dbsc5_rtvram_priv { |
| 26 | void __iomem *regs; |
| 27 | }; |
| 28 | |
| 29 | static int renesas_dbsc5_rtvram_probe(struct udevice *dev) |
| 30 | { |
| 31 | struct renesas_dbsc5_rtvram_priv *priv = dev_get_priv(dev); |
| 32 | u64 addr; |
| 33 | int i; |
| 34 | |
| 35 | /* Set each 4MB from the top of SDRAM as the buffer area of RT-VRAM. */ |
| 36 | for (i = 0; i < RTVRAM_VBUF_NUM; i++) { |
| 37 | addr = (SDRAM_40BIT_ADDR_TOP + (RTVRAM_VBUF_AREA_SIZE * i)) >> 16; |
| 38 | writel(lower_32_bits(addr), priv->regs + (RTVRAM_VBUF_BADDR + (4 * i))); |
| 39 | } |
| 40 | |
| 41 | /* Cache Mode: 8-way, VBF size: 28M */ |
| 42 | setbits_le32(priv->regs + RTVRAM_VBUF_CFG, |
| 43 | RTVRAM_VBUF_CFG_CACHE_MODE_8WAY | RTVRAM_VBUF_CFG_VBUF_SIZE_28M); |
| 44 | |
| 45 | /* Change from Compatible Mode to Extended Mode */ |
| 46 | writel(RTVRAM_EXT_MODE_EXT, priv->regs + RTVRAM_EXT_MODE); |
| 47 | |
| 48 | dsb(); |
| 49 | |
| 50 | return 0; |
| 51 | } |
| 52 | |
| 53 | static int renesas_dbsc5_rtvram_of_to_plat(struct udevice *dev) |
| 54 | { |
| 55 | struct renesas_dbsc5_rtvram_priv *priv = dev_get_priv(dev); |
| 56 | |
| 57 | priv->regs = dev_read_addr_ptr(dev); |
| 58 | if (!priv->regs) |
| 59 | return -EINVAL; |
| 60 | |
| 61 | return 0; |
| 62 | } |
| 63 | |
| 64 | static int renesas_dbsc5_rtvram_get_info(struct udevice *dev, |
| 65 | struct ram_info *info) |
| 66 | { |
| 67 | struct renesas_dbsc5_rtvram_priv *priv = dev_get_priv(dev); |
| 68 | |
| 69 | info->base = (phys_addr_t)priv->regs; |
| 70 | info->size = 28 * SZ_1M; |
| 71 | |
| 72 | return 0; |
| 73 | } |
| 74 | |
| 75 | static const struct ram_ops renesas_dbsc5_rtvram_ops = { |
| 76 | .get_info = renesas_dbsc5_rtvram_get_info, |
| 77 | }; |
| 78 | |
| 79 | static const struct udevice_id renesas_dbsc5_rtvram_ids[] = { |
| 80 | { .compatible = "renesas,r8a779g0-rtvram" }, |
| 81 | { .compatible = "renesas,r8a779h0-rtvram" }, |
| 82 | { /* sentinel */ } |
| 83 | }; |
| 84 | |
| 85 | U_BOOT_DRIVER(renesas_dbsc5_rtvram) = { |
| 86 | .name = "rtvram", |
| 87 | .id = UCLASS_RAM, |
| 88 | .of_match = renesas_dbsc5_rtvram_ids, |
| 89 | .of_to_plat = renesas_dbsc5_rtvram_of_to_plat, |
| 90 | .ops = &renesas_dbsc5_rtvram_ops, |
| 91 | .probe = renesas_dbsc5_rtvram_probe, |
| 92 | .priv_auto = sizeof(struct renesas_dbsc5_rtvram_priv), |
| 93 | }; |