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git01.mediatek.com / filogic / uboot / bf7c0cee160adfa8cbea76491b51fb492d1bf9ba / . / drivers / ram / renesas / dbsc5 / qos.c
blob: 56a60b987afd265ea66831a9ff395a6f7a3d067d [file] [log] [blame]
Marek Vasut1f7ba642024-12-12 14:34:30 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2024 Renesas Electronics Corp.
4 */
5
6#include <asm/io.h>
7#include <dm.h>
8#include <errno.h>
9#include <hang.h>
10#include <linux/sizes.h>
11#include <ram.h>
12#include "dbsc5.h"
13
14/* AXMM */
15#define AXMM_ADSPLCR0 0x4008
16#define AXMM_ADSPLCR1 0x400C
17#define AXMM_ADSPLCR2 0x4010
18#define AXMM_ADSPLCR3 0x4014
19#define AXMM_MMCR 0x4300
20#define AXMM_TR0CR0 0x51000
21#define AXMM_TR1CR0 0x51004
22#define AXMM_TR2CR0 0x51008
23#define AXMM_TR3CR 0x5100C
24#define AXMM_TR3CR0 0x5100C
25#define AXMM_TR0CR1 0x51100
26#define AXMM_TR1CR1 0x51104
27#define AXMM_TR2CR1 0x51108
28#define AXMM_TR3CR1 0x5110C
29#define AXMM_TR0CR2 0x51200
30#define AXMM_TR1CR2 0x51204
31#define AXMM_TR2CR2 0x51208
32#define AXMM_TR3CR2 0x5120C
33
34#define ACTEXT_RT0_R 0xFFC50800
35#define ACTEXT_RT0_W 0xFFC51800
36#define ACTEXT_IR0_R 0xFF890800
37#define ACTEXT_IR0_W 0xFF891800
38#define ACTEXT_IR1_R 0xFF892800
39#define ACTEXT_IR1_W 0xFF893800
40#define SI0_RW_MAX 0xF1201110
41#define SI1_RW_MAX 0xF1202110
42
43/* DBSC */
44#define DBSC_A_CH_OFFSET 0x8000
45#define DBSC_D_CH_OFFSET 0x4000
46
47#define DBSC_SYSCNT0 0x0100
48#define DBSC_SYSCNT1 0x0104
49#define DBSC_FCPRSCTRL 0x0110
50#define DBSC_DBBUS0CNF2 0x0808
51#define DBSC_DBCAM0CNF1 0x0904
52#define DBSC_DBCAM0CNF2 0x0908
53#define DBSC_DBCAM0CNF3 0x090C
54#define DBSC_DBCAMDIS 0x09FC
55#define DBSC_DBSCHCNT0 0x1000
56#define DBSC_DBSCHSZ0 0x1010
57#define DBSC_DBSCHRW0 0x1020
58#define DBSC_SCFCTST2 0x1048
59#define DBSC_DBSCHQOS_0_0 0x1100
60#define DBSC_DBSCHQOS_0_1 0x1104
61#define DBSC_DBSCHQOS_0_2 0x1108
62#define DBSC_DBSCHQOS_0_3 0x110C
63#define DBSC_DBSCHQOS_4_0 0x1140
64#define DBSC_DBSCHQOS_4_1 0x1144
65#define DBSC_DBSCHQOS_4_2 0x1148
66#define DBSC_DBSCHQOS_4_3 0x114C
67#define DBSC_DBSCHQOS_9_0 0x1190
68#define DBSC_DBSCHQOS_9_1 0x1194
69#define DBSC_DBSCHQOS_9_2 0x1198
70#define DBSC_DBSCHQOS_9_3 0x119C
71#define DBSC_DBSCHQOS_12_0 0x11C0
72#define DBSC_DBSCHQOS_12_1 0x11C4
73#define DBSC_DBSCHQOS_12_2 0x11C8
74#define DBSC_DBSCHQOS_12_3 0x11CC
75#define DBSC_DBSCHQOS_13_0 0x11D0
76#define DBSC_DBSCHQOS_13_1 0x11D4
77#define DBSC_DBSCHQOS_13_2 0x11D8
78#define DBSC_DBSCHQOS_13_3 0x11DC
79#define DBSC_DBSCHQOS_14_0 0x11E0
80#define DBSC_DBSCHQOS_14_1 0x11E4
81#define DBSC_DBSCHQOS_14_2 0x11E8
82#define DBSC_DBSCHQOS_14_3 0x11EC
83#define DBSC_DBSCHQOS_15_0 0x11F0
84#define DBSC_DBSCHQOS_15_1 0x11F4
85#define DBSC_DBSCHQOS_15_2 0x11F8
86#define DBSC_DBSCHQOS_15_3 0x11FC
87
88/* CCI */
89#define CCIQOS00 0xC020
90#define CCIQOS01 0xC024
91#define CCIQOS10 0xD000
92#define CCIQOS11 0xD004
93
94/* QOS */
95#define QOS_FIX_QOS_BANK0 0x0
96#define QOS_FIX_QOS_BANK1 0x1000
97#define QOS_BE_QOS_BANK0 0x2000
98#define QOS_BE_QOS_BANK1 0x3000
99#define QOS_SL_INIT 0x8000
100#define QOS_REF_ARS 0x8004
101#define QOS_STATQC 0x8008
102#define QOS_REF_ENBL 0x8044
103#define QOS_BWG 0x804C
104#define QOS_RAS 0x10000
105#define QOS_FSS 0x10048
106#define QOS_RAEN 0x10018
107#define QOS_DANN_LOW 0x10030
108#define QOS_DANN_HIGH 0x10034
109#define QOS_DANT 0x10038
110#define QOS_EMS_LOW 0x10040
111#define QOS_EMS_HIGH 0x10044
112#define QOS_INSFC 0x10050
113#define QOS_EARLYR 0x10060
114#define QOS_RACNT0 0x10080
115#define QOS_STATGEN0 0x10088
116
117#define QOSWT_FIX_QOS_BANK0 0x800
118#define QOSWT_FIX_QOS_BANK1 0x1800
119#define QOSWT_BE_QOS_BANK0 0x2800
120#define QOSWT_BE_QOS_BANK1 0x3800
121#define QOSWT_WTEN 0x8030
122#define QOSWT_WTREF 0x8034
123#define QOSWT_WTSET0 0x8038
124#define QOSWT_WTSET1 0x803C
125
126static const struct {
127 u64 fix;
128 u64 be;
129} g_qosbw_tbl[] = {
130 { 0x000C04010000FFFF, 0x00200030004FFC01 },
131 { 0x000C04010000FFFF, 0x00100030004FFC01 },
132 { 0x000C04010000FFFF, 0x00100030004FFC01 },
133 { 0x000C04010000FFFF, 0x00200030004FFC01 },
134 { 0x000C04010000FFFF, 0x00100030004FFC01 },
135 { 0x000C04010000FFFF, 0x00100030004FFC01 },
136 { 0x000C04010000FFFF, 0x00100030004FFC01 },
137 { 0x000C04010000FFFF, 0x00100030004FFC01 },
138 { 0x000C04010000FFFF, 0x00100030004FFC01 },
139 { 0x000C04010000FFFF, 0x00200030004FFC01 },
140 { 0x000C04010000FFFF, 0x0000000000000000 },
141 { 0x000C04080000FFFF, 0x00200030004FFC01 },
142 { 0x000C04080000FFFF, 0x00100030004FFC01 },
143 { 0x000C04080000FFFF, 0x00100030004FFC01 },
144 { 0x000C04080000FFFF, 0x00100030004FFC01 },
145 { 0x000C04010000FFFF, 0x00200030004FFC01 },
146 { 0x000C04080000FFFF, 0x00100030004FFC01 },
147 { 0x000C04080000FFFF, 0x00100030004FFC01 },
148 { 0x000C04080000FFFF, 0x00100030004FFC01 },
149 { 0x000C04080000FFFF, 0x00100030004FFC01 },
150 { 0x000C04100000FFFF, 0x00100030004FFC01 },
151 { 0x000C04100000FFFF, 0x00100030004FFC01 },
152 { 0x000C04100000FFFF, 0x0000000000000000 },
153 { 0x000C08140000FFFF, 0x00100030004FFC01 },
154 { 0x000C08140000FFFF, 0x00100030004FFC01 },
155 { 0x000000000000FFF0, 0x0000000000000000 },
156 { 0x000C04100000FFFF, 0x00100030004FFC01 },
157 { 0x000C04100000FFFF, 0x00100030004FFC01 },
158 { 0x000C04100000FFFF, 0x0000000000000000 },
159 { 0x000C04080000FFFF, 0x00100030004FFC01 },
160 { 0x000C08140000FFFF, 0x00100030004FFC01 },
161 { 0x000000000000FFFF, 0x0000000000000000 },
162 { 0x000C04080000FFFF, 0x00100030004FFC01 },
163 { 0x000C04080000FFFF, 0x00100030004FFC01 },
164 { 0x000C04080000FFFF, 0x00100030004FFC01 },
165 { 0x000C04080000FFFF, 0x00100030004FFC01 },
166 { 0x000C04080000FFFF, 0x00100030004FFC01 },
167 { 0x000C04080000FFFF, 0x00100030004FFC01 },
168 { 0x001404080000FFFF, 0x00100030004FFC01 },
169 { 0x001404080000FFFF, 0x00100030004FFC01 },
170 { 0x000C04010000FFFF, 0x001000F0004FFC01 },
171 { 0x000C04010000FFFF, 0x001000F0004FFC01 },
172 { 0x000C04010000FFFF, 0x002000F0004FFC01 },
173 { 0x000C04010000FFFF, 0x002000F0004FFC01 },
174 { 0x000000000000FFFF, 0x0000000000000000 },
175 { 0x000000000000FFFF, 0x0000000000000000 },
176 { 0x000000000000FFFF, 0x0000000000000000 },
177 { 0x000000000000FFFF, 0x0000000000000000 },
178 { 0x000C144F0000FFFF, 0x00100030004FFC01 },
179 { 0x000C144F0000FFFF, 0x00100030004FFC01 },
180 { 0x000C144F0000FFFF, 0x00100030004FFC01 },
181 { 0x000C144F0000FFFF, 0x00100030004FFC01 },
182 { 0x000C144F0000FFFF, 0x00100030004FFC01 },
183 { 0x000C144F0000FFFF, 0x00100030004FFC01 },
184 { 0x000000000000FFFF, 0x0000000000000000 },
185 { 0x000C144F0000FFFF, 0x00100030004FFC01 },
186 { 0x000000000000FFFF, 0x0000000000000000 },
187 { 0x000C144F0000FFFF, 0x00100030004FFC01 },
188 { 0x000000000000FFFF, 0x0000000000000000 },
189 { 0x000C144F0000FFFF, 0x00100030004FFC01 },
190 { 0x000000000000FFFF, 0x0000000000000000 },
191 { 0x000000000000FFFF, 0x0000000000000000 },
192 { 0x000C144F0000FFFF, 0x00100030004FFC01 },
193 { 0x000C144F0000FFFF, 0x00100030004FFC01 },
194 { 0x000C04200000FFFF, 0x00100030004FFC01 },
195 { 0x000C04100000FFFF, 0x00100030004FFC01 },
196 { 0x000C144F0000FFFF, 0x00100030004FFC01 },
197 { 0x000C144F0000FFFF, 0x00100030004FFC01 },
198 { 0x000C0C4F0000FFFF, 0x00100030004FFC01 },
199 { 0x000C0C4F0000FFFF, 0x00100030004FFC01 },
200 { 0x001404080000FFFF, 0x00100030004FFC01 },
201 { 0x000C04080000FFFF, 0x00100030004FFC01 },
202 { 0x000C04080000FFFF, 0x00100030004FFC01 },
203 { 0x000C04010000FFFF, 0x00100030004FFC01 },
204 { 0x001424870000FFFF, 0x00100030004FFC01 },
205 { 0x001424870000FFFF, 0x00100030004FFC01 },
206 { 0x000C149E0000FFFF, 0x00100030004FFC01 },
207 { 0x000C149E0000FFFF, 0x00100030004FFC01 },
208 { 0x000000000000FFFF, 0x0000000000000000 },
209 { 0x000000000000FFFF, 0x0000000000000000 },
210 { 0x00140C050000FFFF, 0x00100030004FFC01 },
211 { 0x0014450E0000FFFF, 0x00100030004FFC01 },
212 { 0x001424870000FFFF, 0x00100030004FFC01 },
213 { 0x0014289E0000FFFF, 0x00000000000FFC00 },
214 { 0x0014289E0000FFFF, 0x00000000000FFC00 },
215 { 0x0014149E0000FFFF, 0x0000000000000000 },
216 { 0x000000000000FFFF, 0x0000000000000000 },
217 { 0x000000000000FFFF, 0x0000000000000000 },
218 { 0x001004080000FFFF, 0x0000000000000000 },
219 { 0x001004080000FFFF, 0x0000000000000000 },
220 { 0x001004080000FFFF, 0x0000000000000000 },
221 { 0x000C00000000FFFF, 0x001000F0004FFC01 },
222 { 0x000C00000000FFFF, 0x001000F0004FFC01 },
223 { 0x000C04080000FFFF, 0x00100030004FFC01 },
224 { 0x000C04080000FFFF, 0x00100030004FFC01 },
225 { 0x000000000000FFFF, 0x0000000000000000 },
226 { 0x000C04080000FFFF, 0x00100030004FFC01 },
227 { 0x000C04080000FFFF, 0x00100030004FFC01 },
228 { 0x000C04080000FFFF, 0x00100030004FFC01 },
229 { 0x000000000000FFFF, 0x0000000000000000 },
230 { 0x000C04080000FFFF, 0x00100030004FFC01 },
231 { 0x001404080000FFFF, 0x00100030004FFC01 },
232 { 0x000C04080000FFFF, 0x00100030004FFC01 },
233 { 0x000C04080000FFFF, 0x00100030004FFC01 },
234 { 0x000000000000FFFF, 0x0000000000000000 },
235 { 0x000000000000FFFF, 0x0000000000000000 },
236 { 0x000000000000FFFF, 0x0000000000000000 },
237 { 0x000000000000FFFF, 0x0000000000000000 },
238 { 0x000000000000FFFF, 0x0000000000000000 },
239 { 0x000000000000FFFF, 0x0000000000000000 },
240 { 0x000000000000FFFF, 0x0000000000000000 },
241 { 0x000000000000FFFF, 0x0000000000000000 },
242 { 0x000000000000FFFF, 0x0000000000000000 },
243 { 0x000000000000FFFF, 0x0000000000000000 },
244 { 0x000C04010000FFFF, 0x001001D0004FFC01 },
245 { 0x000000000000FFFF, 0x0000000000000000 },
246 { 0x000C04010000FFFF, 0x001001D0004FFC01 },
247 { 0x000000000000FFFF, 0x0000000000000000 },
248 { 0x000C04010000FFFF, 0x001001D0004FFC01 },
249 { 0x000C04010000FFFF, 0x00100030004FFC01 },
250 { 0x000C04010000FFFF, 0x00100030004FFC01 },
251 { 0x000C04010000FFFF, 0x001001D0004FFC01 },
252 { 0x000C04010000FFFF, 0x00100030004FFC01 },
253 { 0x000C04010000FFFF, 0x00100030004FFC01 },
254 { 0x001404010000FFFF, 0x00100030004FFC01 }
255};
256
257static const struct {
258 u64 fix;
259 u64 be;
260} g_qoswt_tbl[] = {
261 { 0x0000000000000000, 0x0000000000000000 },
262 { 0x0000000000000000, 0x0000000000000000 },
263 { 0x0000000000000000, 0x0000000000000000 },
264 { 0x0000000000000000, 0x0000000000000000 },
265 { 0x0000000000000000, 0x0000000000000000 },
266 { 0x0000000000000000, 0x0000000000000000 },
267 { 0x0000000000000000, 0x0000000000000000 },
268 { 0x0000000000000000, 0x0000000000000000 },
269 { 0x0000000000000000, 0x0000000000000000 },
270 { 0x0000000000000000, 0x0000000000000000 },
271 { 0x0000000000000000, 0x0000000000000000 },
272 { 0x0000000000000000, 0x0000000000000000 },
273 { 0x0000000000000000, 0x0000000000000000 },
274 { 0x0000000000000000, 0x0000000000000000 },
275 { 0x0000000000000000, 0x0000000000000000 },
276 { 0x0000000000000000, 0x0000000000000000 },
277 { 0x0000000000000000, 0x0000000000000000 },
278 { 0x0000000000000000, 0x0000000000000000 },
279 { 0x0000000000000000, 0x0000000000000000 },
280 { 0x0000000000000000, 0x0000000000000000 },
281 { 0x0000000000000000, 0x0000000000000000 },
282 { 0x0000000000000000, 0x0000000000000000 },
283 { 0x0000000000000000, 0x0000000000000000 },
284 { 0x000C04050000FFFF, 0x0000000000000000 },
285 { 0x000C080C0000FFFF, 0x0000000000000000 },
286 { 0x0000000000000000, 0x0000000000000000 },
287 { 0x0000000000000000, 0x0000000000000000 },
288 { 0x0000000000000000, 0x0000000000000000 },
289 { 0x0000000000000000, 0x0000000000000000 },
290 { 0x000C04050000C001, 0x0000000000000000 },
291 { 0x000C080C0000C001, 0x0000000000000000 },
292 { 0x0000000000000000, 0x0000000000000000 },
293 { 0x0000000000000000, 0x0000000000000000 },
294 { 0x0000000000000000, 0x0000000000000000 },
295 { 0x0000000000000000, 0x0000000000000000 },
296 { 0x0000000000000000, 0x0000000000000000 },
297 { 0x0000000000000000, 0x0000000000000000 },
298 { 0x0000000000000000, 0x0000000000000000 },
299 { 0x0000000000000000, 0x0000000000000000 },
300 { 0x0000000000000000, 0x0000000000000000 },
301 { 0x0000000000000000, 0x0000000000000000 },
302 { 0x0000000000000000, 0x0000000000000000 },
303 { 0x0000000000000000, 0x0000000000000000 },
304 { 0x0000000000000000, 0x0000000000000000 },
305 { 0x0000000000000000, 0x0000000000000000 },
306 { 0x0000000000000000, 0x0000000000000000 },
307 { 0x0000000000000000, 0x0000000000000000 },
308 { 0x0000000000000000, 0x0000000000000000 },
309 { 0x0000000000000000, 0x0000000000000000 },
310 { 0x0000000000000000, 0x0000000000000000 },
311 { 0x0000000000000000, 0x0000000000000000 },
312 { 0x0000000000000000, 0x0000000000000000 },
313 { 0x0000000000000000, 0x0000000000000000 },
314 { 0x0000000000000000, 0x0000000000000000 },
315 { 0x0000000000000000, 0x0000000000000000 },
316 { 0x0000000000000000, 0x0000000000000000 },
317 { 0x0000000000000000, 0x0000000000000000 },
318 { 0x0000000000000000, 0x0000000000000000 },
319 { 0x0000000000000000, 0x0000000000000000 },
320 { 0x0000000000000000, 0x0000000000000000 },
321 { 0x0000000000000000, 0x0000000000000000 },
322 { 0x0000000000000000, 0x0000000000000000 },
323 { 0x0000000000000000, 0x0000000000000000 },
324 { 0x0000000000000000, 0x0000000000000000 },
325 { 0x0000000000000000, 0x0000000000000000 },
326 { 0x0000000000000000, 0x0000000000000000 },
327 { 0x0000000000000000, 0x0000000000000000 },
328 { 0x0000000000000000, 0x0000000000000000 },
329 { 0x0000000000000000, 0x0000000000000000 },
330 { 0x0000000000000000, 0x0000000000000000 },
331 { 0x0000000000000000, 0x0000000000000000 },
332 { 0x0000000000000000, 0x0000000000000000 },
333 { 0x0000000000000000, 0x0000000000000000 },
334 { 0x0000000000000000, 0x0000000000000000 },
335 { 0x001424870000C001, 0x0000000000000000 },
336 { 0x001424870000C001, 0x0000000000000000 },
337 { 0x0000000000000000, 0x0000000000000000 },
338 { 0x0000000000000000, 0x0000000000000000 },
339 { 0x0000000000000000, 0x0000000000000000 },
340 { 0x0000000000000000, 0x0000000000000000 },
341 { 0x0000000000000000, 0x0000000000000000 },
342 { 0x0000000000000000, 0x0000000000000000 },
343 { 0x001424870000FFFF, 0x0000000000000000 },
344 { 0x0000000000000000, 0x0000000000000000 },
345 { 0x0000000000000000, 0x0000000000000000 },
346 { 0x0000000000000000, 0x0000000000000000 },
347 { 0x0000000000000000, 0x0000000000000000 },
348 { 0x0000000000000000, 0x0000000000000000 },
349 { 0x0000000000000000, 0x0000000000000000 },
350 { 0x0000000000000000, 0x0000000000000000 },
351 { 0x0000000000000000, 0x0000000000000000 },
352 { 0x0000000000000000, 0x0000000000000000 },
353 { 0x0000000000000000, 0x0000000000000000 },
354 { 0x0000000000000000, 0x0000000000000000 },
355 { 0x0000000000000000, 0x0000000000000000 },
356 { 0x0000000000000000, 0x0000000000000000 },
357 { 0x0000000000000000, 0x0000000000000000 },
358 { 0x0000000000000000, 0x0000000000000000 },
359 { 0x0000000000000000, 0x0000000000000000 },
360 { 0x0000000000000000, 0x0000000000000000 },
361 { 0x0000000000000000, 0x0000000000000000 },
362 { 0x0000000000000000, 0x0000000000000000 },
363 { 0x0000000000000000, 0x0000000000000000 },
364 { 0x0000000000000000, 0x0000000000000000 },
365 { 0x0000000000000000, 0x0000000000000000 },
366 { 0x0000000000000000, 0x0000000000000000 },
367 { 0x0000000000000000, 0x0000000000000000 },
368 { 0x0000000000000000, 0x0000000000000000 },
369 { 0x0000000000000000, 0x0000000000000000 },
370 { 0x0000000000000000, 0x0000000000000000 },
371 { 0x0000000000000000, 0x0000000000000000 },
372 { 0x0000000000000000, 0x0000000000000000 },
373 { 0x0000000000000000, 0x0000000000000000 },
374 { 0x0000000000000000, 0x0000000000000000 },
375 { 0x0000000000000000, 0x0000000000000000 },
376 { 0x0000000000000000, 0x0000000000000000 },
377 { 0x0000000000000000, 0x0000000000000000 },
378 { 0x0000000000000000, 0x0000000000000000 },
379 { 0x0000000000000000, 0x0000000000000000 },
380 { 0x0000000000000000, 0x0000000000000000 },
381 { 0x0000000000000000, 0x0000000000000000 },
382 { 0x0000000000000000, 0x0000000000000000 },
383 { 0x0000000000000000, 0x0000000000000000 },
384 { 0x0000000000000000, 0x0000000000000000 },
385 { 0x0000000000000000, 0x0000000000000000 }
386};
387
388struct renesas_dbsc5_qos_priv {
389 void __iomem *regs;
390};
391
392static int dbsc5_qos_dbsc_setting(struct udevice *dev)
393{
394 struct renesas_dbsc5_qos_priv *priv = dev_get_priv(dev);
395 void __iomem *regs_dbsc_a, *regs_dbsc_d;
396 unsigned int ch, nch;
397
398 if (IS_ENABLED(CONFIG_R8A779G0) &&
399 renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779G0)
400 nch = 2;
401 else if (IS_ENABLED(CONFIG_R8A779H0) &&
402 renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779H0)
403 nch = 1;
404 else
405 return -EINVAL;
406
407 for (ch = 0; ch < nch; ch++) {
408 regs_dbsc_a = priv->regs + DBSC5_DBSC_A_OFFSET + ch * DBSC_A_CH_OFFSET;
409 regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET + ch * DBSC_D_CH_OFFSET;
410
411 /* DBSC CAM, Scheduling Setting */
412 writel(0x1234, regs_dbsc_d + DBSC_SYSCNT0);
413 writel(0x1234, regs_dbsc_a + DBSC_SYSCNT0);
414 writel(0x48218, regs_dbsc_a + DBSC_DBCAM0CNF1);
415 writel(0x1C4, regs_dbsc_a + DBSC_DBCAM0CNF2);
416 writel(0x3, regs_dbsc_a + DBSC_DBCAM0CNF3);
417
418 if (IS_ENABLED(CONFIG_R8A779G0) &&
419 renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779G0 &&
420 (renesas_get_cpu_rev_integer() < 2 ||
421 (renesas_get_cpu_rev_integer() == 2 &&
422 renesas_get_cpu_rev_fraction() <= 1))) {
423 /* OTLINT-5579: V4H <= rev2.1 DBSC W/A-3 */
424 writel(0x11, regs_dbsc_a + DBSC_DBCAMDIS);
425 } else {
426 writel(0x10, regs_dbsc_a + DBSC_DBCAMDIS);
427 }
428
429 writel(0xF0037, regs_dbsc_a + DBSC_DBSCHCNT0);
430 writel(0x1, regs_dbsc_a + DBSC_DBSCHSZ0);
431 writel(0xF7311111, regs_dbsc_a + DBSC_DBSCHRW0);
432 writel(0x111F1FFF, regs_dbsc_a + DBSC_SCFCTST2);
433
434 /* OTLINT-5579: V4H DBSC WA3 */
435 writel(0x7, regs_dbsc_a + DBSC_DBBUS0CNF2);
436
437 /* DBSC QoS Setting */
438 writel(0xFFFF, regs_dbsc_a + DBSC_DBSCHQOS_0_0);
439 writel(0x480, regs_dbsc_a + DBSC_DBSCHQOS_0_1);
440 writel(0x300, regs_dbsc_a + DBSC_DBSCHQOS_0_2);
441 writel(0x180, regs_dbsc_a + DBSC_DBSCHQOS_0_3);
442 writel(0x400, regs_dbsc_a + DBSC_DBSCHQOS_4_0);
443 writel(0x300, regs_dbsc_a + DBSC_DBSCHQOS_4_1);
444 writel(0x200, regs_dbsc_a + DBSC_DBSCHQOS_4_2);
445 writel(0x100, regs_dbsc_a + DBSC_DBSCHQOS_4_3);
446 writel(0x300, regs_dbsc_a + DBSC_DBSCHQOS_9_0);
447 writel(0x240, regs_dbsc_a + DBSC_DBSCHQOS_9_1);
448 writel(0x180, regs_dbsc_a + DBSC_DBSCHQOS_9_2);
449 writel(0xC0, regs_dbsc_a + DBSC_DBSCHQOS_9_3);
450 writel(0x40, regs_dbsc_a + DBSC_DBSCHQOS_12_0);
451 writel(0x30, regs_dbsc_a + DBSC_DBSCHQOS_12_1);
452 writel(0x20, regs_dbsc_a + DBSC_DBSCHQOS_12_2);
453 writel(0x10, regs_dbsc_a + DBSC_DBSCHQOS_12_3);
454 writel(0x300, regs_dbsc_a + DBSC_DBSCHQOS_13_0);
455 writel(0x240, regs_dbsc_a + DBSC_DBSCHQOS_13_1);
456 writel(0x180, regs_dbsc_a + DBSC_DBSCHQOS_13_2);
457 writel(0xC0, regs_dbsc_a + DBSC_DBSCHQOS_13_3);
458 writel(0x200, regs_dbsc_a + DBSC_DBSCHQOS_14_0);
459 writel(0x180, regs_dbsc_a + DBSC_DBSCHQOS_14_1);
460 writel(0x100, regs_dbsc_a + DBSC_DBSCHQOS_14_2);
461 writel(0x80, regs_dbsc_a + DBSC_DBSCHQOS_14_3);
462 writel(0x100, regs_dbsc_a + DBSC_DBSCHQOS_15_0);
463 writel(0xC0, regs_dbsc_a + DBSC_DBSCHQOS_15_1);
464 writel(0x80, regs_dbsc_a + DBSC_DBSCHQOS_15_2);
465 writel(0x40, regs_dbsc_a + DBSC_DBSCHQOS_15_3);
466
467 /* Target register is only DBSC0 side. */
468 if (ch == 0)
469 writel(0x1, regs_dbsc_a + DBSC_FCPRSCTRL);
470
471 writel(0x1, regs_dbsc_a + DBSC_SYSCNT1);
472 writel(0x0, regs_dbsc_d + DBSC_SYSCNT0);
473 writel(0x0, regs_dbsc_a + DBSC_SYSCNT0);
474 }
475
476 return 0;
477}
478
479static int dbsc5_qos_settings_init(struct udevice *dev)
480{
481 struct renesas_dbsc5_qos_priv *priv = dev_get_priv(dev);
482 void __iomem *regs_axmm = priv->regs + DBSC5_AXMM_OFFSET;
483 void __iomem *regs_cci = priv->regs + DBSC5_CCI_OFFSET;
484 void __iomem *regs_qos = priv->regs + DBSC5_QOS_OFFSET;
485 int i;
486
487 if (IS_ENABLED(CONFIG_R8A779G0) &&
488 renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779G0) {
489 /* Address Split 2ch */
490 writel(0x0, regs_axmm + AXMM_ADSPLCR0);
491 writel(0xFF1B0C, regs_axmm + AXMM_ADSPLCR1);
492 writel(0x0, regs_axmm + AXMM_ADSPLCR2);
493 writel(0x0, regs_axmm + AXMM_ADSPLCR3);
494
495 writel(0x8000000, regs_cci + CCIQOS00);
496 writel(0x8000000, regs_cci + CCIQOS01);
497
498 if (renesas_get_cpu_rev_integer() >= 2) {
499 writel(0x1, regs_cci + CCIQOS10);
500 writel(0x1, regs_cci + CCIQOS11);
501 } else {
502 writel(0x0, regs_cci + CCIQOS10);
503 writel(0x0, regs_cci + CCIQOS11);
504 }
505
506 /* Resource Alloc setting */
507 writel(0x48, regs_qos + QOS_RAS);
508 } else if (IS_ENABLED(CONFIG_R8A779H0) &&
509 renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779H0) {
510 /* Resource Alloc setting */
511 writel(0x30, regs_qos + QOS_RAS);
512 } else {
513 return -EINVAL;
514 }
515
516 writel(0x2020201, regs_qos + QOS_DANN_LOW);
517 writel(0x4040200, regs_qos + QOS_DANN_HIGH);
518 writel(0x181008, regs_qos + QOS_DANT);
519 writel(0x0, regs_qos + QOS_EMS_LOW);
520 writel(0x0, regs_qos + QOS_EMS_HIGH);
521 writel(0xA, regs_qos + QOS_FSS);
522 writel(0x30F0001, regs_qos + QOS_INSFC);
523 writel(0x0, regs_qos + QOS_EARLYR);
524 writel(0x50003, regs_qos + QOS_RACNT0);
525 writel(0x0, regs_qos + QOS_STATGEN0);
526
527 /* QoS MSTAT setting */
528 writel(0x70120, regs_qos + QOS_SL_INIT);
529 writel(0x11B0000, regs_qos + QOS_REF_ARS);
530 writel(0x12, regs_qos + QOS_REF_ENBL);
531 writel(0x4, regs_qos + QOS_BWG);
532
533 if (IS_ENABLED(CONFIG_R8A779G0) &&
534 renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779G0 &&
535 (renesas_get_cpu_rev_integer() < 2 ||
536 (renesas_get_cpu_rev_integer() == 2 &&
537 renesas_get_cpu_rev_fraction() <= 1))) {
538 /* OTLINT-5579: V4H <= rev2.1 DBSC W/A-3 */
539 writel(0x0, regs_axmm + AXMM_MMCR);
540 } else {
541 writel(0x10000, regs_axmm + AXMM_MMCR);
542 }
543
544 writel(0x3, ACTEXT_RT0_R);
545 writel(0x3, ACTEXT_RT0_W);
546
547 /*
548 * This may be necessary, but this IP is powered off at this point:
549 * writel(0x3, ACTEXT_IR0_R);
550 * writel(0x3, ACTEXT_IR0_W);
551 * writel(0x3, ACTEXT_IR1_R);
552 * writel(0x3, ACTEXT_IR1_W);
553 */
554
555 if (IS_ENABLED(CONFIG_R8A779G0) &&
556 renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779G0) {
557 writel(0x10000, regs_axmm + AXMM_TR3CR);
558
559 if (renesas_get_cpu_rev_integer() >= 2) {
560 /* WA1 patch for IPL CA76 hang-up issue, REL_TRI_DN-7592 */
561 writel(0x38, SI0_RW_MAX);
562 writel(0x38, SI1_RW_MAX);
563 }
564 }
565
566 if (IS_ENABLED(CONFIG_R8A779H0) &&
567 renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779H0) {
568 writel(0x0, regs_axmm + AXMM_TR0CR0);
569 writel(0x0, regs_axmm + AXMM_TR1CR0);
570 writel(0x0, regs_axmm + AXMM_TR2CR0);
571 writel(0x0, regs_axmm + AXMM_TR3CR0);
572 writel(0x70707070, regs_axmm + AXMM_TR0CR1);
573 writel(0x70707070, regs_axmm + AXMM_TR1CR1);
574 writel(0x70707070, regs_axmm + AXMM_TR2CR1);
575 writel(0x70707070, regs_axmm + AXMM_TR3CR1);
576 writel(0x70707070, regs_axmm + AXMM_TR0CR2);
577 writel(0x70707070, regs_axmm + AXMM_TR1CR2);
578 writel(0x70707070, regs_axmm + AXMM_TR2CR2);
579 writel(0x70707070, regs_axmm + AXMM_TR3CR2);
580 }
581
582 for (i = 0U; i < ARRAY_SIZE(g_qosbw_tbl); i++) {
583 writeq(g_qosbw_tbl[i].fix, regs_qos + QOS_FIX_QOS_BANK0 + (i * 8));
584 writeq(g_qosbw_tbl[i].fix, regs_qos + QOS_FIX_QOS_BANK1 + (i * 8));
585 writeq(g_qosbw_tbl[i].be, regs_qos + QOS_BE_QOS_BANK0 + (i * 8));
586 writeq(g_qosbw_tbl[i].be, regs_qos + QOS_BE_QOS_BANK1 + (i * 8));
587 }
588
589 for (i = 0U; i < ARRAY_SIZE(g_qoswt_tbl); i++) {
590 writeq(g_qoswt_tbl[i].fix, regs_qos + QOSWT_FIX_QOS_BANK0 + (i * 8));
591 writeq(g_qoswt_tbl[i].fix, regs_qos + QOSWT_FIX_QOS_BANK1 + (i * 8));
592 writeq(g_qoswt_tbl[i].be, regs_qos + QOSWT_BE_QOS_BANK0 + (i * 8));
593 writeq(g_qoswt_tbl[i].be, regs_qos + QOSWT_BE_QOS_BANK1 + (i * 8));
594 }
595
596 /* QoS SRAM setting */
597 writel(0x1, regs_qos + QOS_RAEN);
598 writel(0x2080208, regs_qos + QOSWT_WTREF);
599 writel(0xD90050F, regs_qos + QOSWT_WTSET0);
600 writel(0xD90050F, regs_qos + QOSWT_WTSET1);
601 writel(0x1, regs_qos + QOSWT_WTEN);
602 writel(0x101, regs_qos + QOS_STATQC);
603
604 return 0;
605}
606
607static int renesas_dbsc5_qos_probe(struct udevice *dev)
608{
609 int ret;
610
611 /* Setting the register of DBSC4 for QoS initialize */
612 ret = dbsc5_qos_dbsc_setting(dev);
613 if (ret)
614 return ret;
615
616 return dbsc5_qos_settings_init(dev);
617}
618
619static int renesas_dbsc5_qos_of_to_plat(struct udevice *dev)
620{
621 struct renesas_dbsc5_qos_priv *priv = dev_get_priv(dev);
622
623 priv->regs = dev_read_addr_ptr(dev);
624 if (!priv->regs)
625 return -EINVAL;
626
627 return 0;
628}
629
630U_BOOT_DRIVER(renesas_dbsc5_qos) = {
631 .name = "dbsc5_qos",
632 .id = UCLASS_NOP,
633 .of_to_plat = renesas_dbsc5_qos_of_to_plat,
634 .probe = renesas_dbsc5_qos_probe,
635 .priv_auto = sizeof(struct renesas_dbsc5_qos_priv),
636};