| Marek Vasut | 1f7ba64 | 2024-12-12 14:34:30 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2024 Renesas Electronics Corp. |
| 4 | */ |
| 5 | |
| 6 | #ifndef __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__ |
| 7 | #define __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__ |
| 8 | |
| 9 | /* |
| 10 | * DBSC5 ... 0xe678_0000..0xe67fffff |
| 11 | * - AXMM_BASE 0xe6780000 MM (DDR Hier) MM AXI Router - Region 0 |
| 12 | * - DBSC_A_BASE 0xe6790000 MM (DDR Hier) DBSC0A - Region 0 |
| 13 | * - CCI_BASE 0xe67A0000 MM (DDR Hier) FBA for MM |
| 14 | * - DBSC_D_BASE 0xE67A4000 MM (DDR Hier) DBSC0D - Region 0 |
| 15 | * - QOS_BASE 0xe67E0000 MM (DDR Hier) M-STATQ (64kiB) |
| 16 | */ |
| 17 | #define DBSC5_AXMM_OFFSET 0x00000 |
| 18 | #define DBSC5_DBSC_A_OFFSET 0x10000 |
| 19 | #define DBSC5_CCI_OFFSET 0x20000 |
| 20 | #define DBSC5_DBSC_D_OFFSET 0x24000 |
| 21 | #define DBSC5_QOS_OFFSET 0x60000 |
| 22 | |
| 23 | struct renesas_dbsc5_data { |
| 24 | const char *clock_node; |
| 25 | const char *reset_node; |
| 26 | }; |
| 27 | |
| 28 | #endif /* __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__ */ |