Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / bf7c0cee160adfa8cbea76491b51fb492d1bf9ba / . / drivers / pinctrl / renesas / pfc-r8a7792.c
blob: d2ff1d9d1a699c9eb1c10241317a93d11ece9094 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2/*
3 * r8a7792 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2013-2014 Renesas Electronics Corporation
6 * Copyright (C) 2016 Cogent Embedded, Inc., <source@cogentembedded.com>
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]7 */
8
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]9#include <dm.h>
10#include <errno.h>
11#include <dm/pinctrl.h>
12#include <linux/kernel.h>
13
14#include "sh_pfc.h"
15
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]16#define CPU_ALL_GP(fn, sfx) \
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]17 PORT_GP_CFG_29(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
18 PORT_GP_CFG_23(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
19 PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
20 PORT_GP_CFG_28(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
21 PORT_GP_CFG_17(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
22 PORT_GP_CFG_17(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
23 PORT_GP_CFG_17(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
24 PORT_GP_CFG_17(7, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
25 PORT_GP_CFG_17(8, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
26 PORT_GP_CFG_17(9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
27 PORT_GP_CFG_32(10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
28 PORT_GP_CFG_30(11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
29
30#define CPU_ALL_NOGP(fn) \
31 PIN_NOGP_CFG(DU0_DOTCLKIN, "DU0_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP), \
32 PIN_NOGP_CFG(DU0_DOTCLKOUT, "DU0_DOTCLKOUT", fn, SH_PFC_PIN_CFG_PULL_UP), \
33 PIN_NOGP_CFG(DU1_DOTCLKIN, "DU1_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP), \
34 PIN_NOGP_CFG(DU1_DOTCLKOUT, "DU1_DOTCLKOUT", fn, SH_PFC_PIN_CFG_PULL_UP), \
35 PIN_NOGP_CFG(EDBGREQ, "EDBGREQ", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
36 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
37 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
38 PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
39 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]40
41enum {
42 PINMUX_RESERVED = 0,
43
44 PINMUX_DATA_BEGIN,
45 GP_ALL(DATA),
46 PINMUX_DATA_END,
47
48 PINMUX_FUNCTION_BEGIN,
49 GP_ALL(FN),
50
51 /* GPSR0 */
52 FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
53 FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
54 FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_16,
55 FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20, FN_IP0_21,
56 FN_IP0_22, FN_IP0_23, FN_IP1_0, FN_IP1_1, FN_IP1_2,
57 FN_IP1_3, FN_IP1_4,
58
59 /* GPSR1 */
60 FN_IP1_5, FN_IP1_6, FN_IP1_7, FN_IP1_8, FN_IP1_9, FN_IP1_10,
61 FN_IP1_11, FN_IP1_12, FN_IP1_13, FN_IP1_14, FN_IP1_15, FN_IP1_16,
62 FN_DU1_DB2_C0_DATA12, FN_DU1_DB3_C1_DATA13, FN_DU1_DB4_C2_DATA14,
63 FN_DU1_DB5_C3_DATA15, FN_DU1_DB6_C4, FN_DU1_DB7_C5,
64 FN_DU1_EXHSYNC_DU1_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC,
65 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_DU1_DISP, FN_DU1_CDE,
66
67 /* GPSR2 */
68 FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7,
69 FN_D8, FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
70 FN_A0, FN_A1, FN_A2, FN_A3, FN_A4, FN_A5, FN_A6, FN_A7,
71 FN_A8, FN_A9, FN_A10, FN_A11, FN_A12, FN_A13, FN_A14, FN_A15,
72
73 /* GPSR3 */
74 FN_A16, FN_A17, FN_A18, FN_A19, FN_IP1_17, FN_IP1_18,
75 FN_CS1_N_A26, FN_EX_CS0_N, FN_EX_CS1_N, FN_EX_CS2_N, FN_EX_CS3_N,
76 FN_EX_CS4_N, FN_EX_CS5_N, FN_BS_N, FN_RD_N, FN_RD_WR_N,
77 FN_WE0_N, FN_WE1_N, FN_EX_WAIT0, FN_IRQ0, FN_IRQ1, FN_IRQ2, FN_IRQ3,
78 FN_IP1_19, FN_IP1_20, FN_IP1_21, FN_IP1_22, FN_CS0_N,
79
80 /* GPSR4 */
81 FN_VI0_CLK, FN_VI0_CLKENB, FN_VI0_HSYNC_N, FN_VI0_VSYNC_N,
82 FN_VI0_D0_B0_C0, FN_VI0_D1_B1_C1, FN_VI0_D2_B2_C2, FN_VI0_D3_B3_C3,
83 FN_VI0_D4_B4_C4, FN_VI0_D5_B5_C5, FN_VI0_D6_B6_C6, FN_VI0_D7_B7_C7,
84 FN_VI0_D8_G0_Y0, FN_VI0_D9_G1_Y1, FN_VI0_D10_G2_Y2, FN_VI0_D11_G3_Y3,
85 FN_VI0_FIELD,
86
87 /* GPSR5 */
88 FN_VI1_CLK, FN_VI1_CLKENB, FN_VI1_HSYNC_N, FN_VI1_VSYNC_N,
89 FN_VI1_D0_B0_C0, FN_VI1_D1_B1_C1, FN_VI1_D2_B2_C2, FN_VI1_D3_B3_C3,
90 FN_VI1_D4_B4_C4, FN_VI1_D5_B5_C5, FN_VI1_D6_B6_C6, FN_VI1_D7_B7_C7,
91 FN_VI1_D8_G0_Y0, FN_VI1_D9_G1_Y1, FN_VI1_D10_G2_Y2, FN_VI1_D11_G3_Y3,
92 FN_VI1_FIELD,
93
94 /* GPSR6 */
95 FN_IP2_0, FN_IP2_1, FN_IP2_2, FN_IP2_3, FN_IP2_4, FN_IP2_5, FN_IP2_6,
96 FN_IP2_7, FN_IP2_8, FN_IP2_9, FN_IP2_10, FN_IP2_11, FN_IP2_12,
97 FN_IP2_13, FN_IP2_14, FN_IP2_15, FN_IP2_16,
98
99 /* GPSR7 */
100 FN_IP3_0, FN_IP3_1, FN_IP3_2, FN_IP3_3, FN_IP3_4, FN_IP3_5, FN_IP3_6,
101 FN_IP3_7, FN_IP3_8, FN_IP3_9, FN_IP3_10, FN_IP3_11, FN_IP3_12,
102 FN_IP3_13, FN_VI3_D10_Y2, FN_IP3_14, FN_VI3_FIELD,
103
104 /* GPSR8 */
105 FN_VI4_CLK, FN_IP4_0, FN_IP4_1, FN_IP4_3_2, FN_IP4_4, FN_IP4_6_5,
106 FN_IP4_8_7, FN_IP4_10_9, FN_IP4_12_11, FN_IP4_14_13, FN_IP4_16_15,
107 FN_IP4_18_17, FN_IP4_20_19, FN_IP4_21, FN_IP4_22, FN_IP4_23, FN_IP4_24,
108
109 /* GPSR9 */
110 FN_VI5_CLK, FN_IP5_0, FN_IP5_1, FN_IP5_2, FN_IP5_3, FN_IP5_4, FN_IP5_5,
111 FN_IP5_6, FN_IP5_7, FN_IP5_8, FN_IP5_9, FN_IP5_10, FN_IP5_11,
112 FN_VI5_D9_Y1, FN_VI5_D10_Y2, FN_VI5_D11_Y3, FN_VI5_FIELD,
113
114 /* GPSR10 */
115 FN_IP6_0, FN_IP6_1, FN_HRTS0_N, FN_IP6_2, FN_IP6_3, FN_IP6_4, FN_IP6_5,
116 FN_HCTS1_N, FN_IP6_6, FN_IP6_7, FN_SCK0, FN_CTS0_N, FN_RTS0_N,
117 FN_TX0, FN_RX0, FN_SCK1, FN_CTS1_N, FN_RTS1_N, FN_TX1, FN_RX1,
118 FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_16,
119 FN_IP6_18_17, FN_SCIF_CLK, FN_CAN0_TX, FN_CAN0_RX, FN_CAN_CLK,
120 FN_CAN1_TX, FN_CAN1_RX,
121
122 /* GPSR11 */
123 FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_6, FN_IP7_7, FN_SD0_CLK,
124 FN_SD0_CMD, FN_SD0_DAT0, FN_SD0_DAT1, FN_SD0_DAT2, FN_SD0_DAT3,
125 FN_SD0_CD, FN_SD0_WP, FN_IP7_9_8, FN_IP7_11_10, FN_IP7_13_12,
126 FN_IP7_15_14, FN_IP7_16, FN_IP7_17, FN_IP7_18, FN_IP7_19, FN_IP7_20,
127 FN_ADICLK, FN_ADICS_SAMP, FN_ADIDATA, FN_ADICHS0, FN_ADICHS1,
128 FN_ADICHS2, FN_AVS1, FN_AVS2,
129
130 /* IPSR0 */
131 FN_DU0_DR0_DATA0, FN_DU0_DR1_DATA1, FN_DU0_DR2_Y4_DATA2,
132 FN_DU0_DR3_Y5_DATA3, FN_DU0_DR4_Y6_DATA4, FN_DU0_DR5_Y7_DATA5,
133 FN_DU0_DR6_Y8_DATA6, FN_DU0_DR7_Y9_DATA7, FN_DU0_DG0_DATA8,
134 FN_DU0_DG1_DATA9, FN_DU0_DG2_C6_DATA10, FN_DU0_DG3_C7_DATA11,
135 FN_DU0_DG4_Y0_DATA12, FN_DU0_DG5_Y1_DATA13, FN_DU0_DG6_Y2_DATA14,
136 FN_DU0_DG7_Y3_DATA15, FN_DU0_DB0, FN_DU0_DB1, FN_DU0_DB2_C0,
137 FN_DU0_DB3_C1, FN_DU0_DB4_C2, FN_DU0_DB5_C3, FN_DU0_DB6_C4,
138 FN_DU0_DB7_C5,
139
140 /* IPSR1 */
141 FN_DU0_EXHSYNC_DU0_HSYNC, FN_DU0_EXVSYNC_DU0_VSYNC,
142 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_DU0_DISP, FN_DU0_CDE,
143 FN_DU1_DR2_Y4_DATA0, FN_DU1_DR3_Y5_DATA1, FN_DU1_DR4_Y6_DATA2,
144 FN_DU1_DR5_Y7_DATA3, FN_DU1_DR6_DATA4, FN_DU1_DR7_DATA5,
145 FN_DU1_DG2_C6_DATA6, FN_DU1_DG3_C7_DATA7, FN_DU1_DG4_Y0_DATA8,
146 FN_DU1_DG5_Y1_DATA9, FN_DU1_DG6_Y2_DATA10, FN_DU1_DG7_Y3_DATA11,
147 FN_A20, FN_MOSI_IO0, FN_A21, FN_MISO_IO1, FN_A22, FN_IO2,
148 FN_A23, FN_IO3, FN_A24, FN_SPCLK, FN_A25, FN_SSL,
149
150 /* IPSR2 */
151 FN_VI2_CLK, FN_AVB_RX_CLK, FN_VI2_CLKENB, FN_AVB_RX_DV,
152 FN_VI2_HSYNC_N, FN_AVB_RXD0, FN_VI2_VSYNC_N, FN_AVB_RXD1,
153 FN_VI2_D0_C0, FN_AVB_RXD2, FN_VI2_D1_C1, FN_AVB_RXD3,
154 FN_VI2_D2_C2, FN_AVB_RXD4, FN_VI2_D3_C3, FN_AVB_RXD5,
155 FN_VI2_D4_C4, FN_AVB_RXD6, FN_VI2_D5_C5, FN_AVB_RXD7,
156 FN_VI2_D6_C6, FN_AVB_RX_ER, FN_VI2_D7_C7, FN_AVB_COL,
157 FN_VI2_D8_Y0, FN_AVB_TXD3, FN_VI2_D9_Y1, FN_AVB_TX_EN,
158 FN_VI2_D10_Y2, FN_AVB_TXD0, FN_VI2_D11_Y3, FN_AVB_TXD1,
159 FN_VI2_FIELD, FN_AVB_TXD2,
160
161 /* IPSR3 */
162 FN_VI3_CLK, FN_AVB_TX_CLK, FN_VI3_CLKENB, FN_AVB_TXD4,
163 FN_VI3_HSYNC_N, FN_AVB_TXD5, FN_VI3_VSYNC_N, FN_AVB_TXD6,
164 FN_VI3_D0_C0, FN_AVB_TXD7, FN_VI3_D1_C1, FN_AVB_TX_ER,
165 FN_VI3_D2_C2, FN_AVB_GTX_CLK, FN_VI3_D3_C3, FN_AVB_MDC,
166 FN_VI3_D4_C4, FN_AVB_MDIO, FN_VI3_D5_C5, FN_AVB_LINK,
167 FN_VI3_D6_C6, FN_AVB_MAGIC, FN_VI3_D7_C7, FN_AVB_PHY_INT,
168 FN_VI3_D8_Y0, FN_AVB_CRS, FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
169 FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
170
171 /* IPSR4 */
172 FN_VI4_CLKENB, FN_VI0_D12_G4_Y4, FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
173 FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, FN_RDR_CLKOUT,
174 FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
175 FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4,
176 FN_VI4_D2_C2, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
177 FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6,
178 FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7,
179 FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4,
180 FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5,
181 FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6,
182 FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7,
183 FN_VI4_D9_Y1, FN_VI3_D12_Y4, FN_VI4_D10_Y2, FN_VI3_D13_Y5,
184 FN_VI4_D11_Y3, FN_VI3_D14_Y6, FN_VI4_FIELD, FN_VI3_D15_Y7,
185
186 /* IPSR5 */
187 FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B, FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
188 FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B, FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
189 FN_VI5_D1_C1, FN_VI1_D16_R0, FN_VI5_D2_C2, FN_VI1_D17_R1,
190 FN_VI5_D3_C3, FN_VI1_D18_R2, FN_VI5_D4_C4, FN_VI1_D19_R3,
191 FN_VI5_D5_C5, FN_VI1_D20_R4, FN_VI5_D6_C6, FN_VI1_D21_R5,
192 FN_VI5_D7_C7, FN_VI1_D22_R6, FN_VI5_D8_Y0, FN_VI1_D23_R7,
193
194 /* IPSR6 */
195 FN_MSIOF0_SCK, FN_HSCK0, FN_MSIOF0_SYNC, FN_HCTS0_N,
196 FN_MSIOF0_TXD, FN_HTX0, FN_MSIOF0_RXD, FN_HRX0,
197 FN_MSIOF1_SCK, FN_HSCK1, FN_MSIOF1_SYNC, FN_HRTS1_N,
198 FN_MSIOF1_TXD, FN_HTX1, FN_MSIOF1_RXD, FN_HRX1,
199 FN_DRACK0, FN_SCK2, FN_DACK0, FN_TX2, FN_DREQ0_N, FN_RX2,
200 FN_DACK1, FN_SCK3, FN_TX3, FN_DREQ1_N, FN_RX3,
201
202 /* IPSR7 */
203 FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, FN_PWM1, FN_TCLK2, FN_FSO_CFE_1,
204 FN_PWM2, FN_TCLK3, FN_FSO_TOE, FN_PWM3, FN_PWM4,
205 FN_SSI_SCK34, FN_TPU0TO0, FN_SSI_WS34, FN_TPU0TO1,
206 FN_SSI_SDATA3, FN_TPU0TO2, FN_SSI_SCK4, FN_TPU0TO3,
207 FN_SSI_WS4, FN_SSI_SDATA4, FN_AUDIO_CLKOUT,
208 FN_AUDIO_CLKA, FN_AUDIO_CLKB,
209
210 /* MOD_SEL */
211 FN_SEL_VI1_0, FN_SEL_VI1_1,
212 PINMUX_FUNCTION_END,
213
214 PINMUX_MARK_BEGIN,
215 DU1_DB2_C0_DATA12_MARK, DU1_DB3_C1_DATA13_MARK,
216 DU1_DB4_C2_DATA14_MARK, DU1_DB5_C3_DATA15_MARK,
217 DU1_DB6_C4_MARK, DU1_DB7_C5_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
218 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
219 DU1_DISP_MARK, DU1_CDE_MARK,
220
221 D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK, D6_MARK,
222 D7_MARK, D8_MARK, D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK,
223 D14_MARK, D15_MARK, A0_MARK, A1_MARK, A2_MARK, A3_MARK, A4_MARK,
224 A5_MARK, A6_MARK, A7_MARK, A8_MARK, A9_MARK, A10_MARK, A11_MARK,
225 A12_MARK, A13_MARK, A14_MARK, A15_MARK,
226
227 A16_MARK, A17_MARK, A18_MARK, A19_MARK, CS1_N_A26_MARK,
228 EX_CS0_N_MARK, EX_CS1_N_MARK, EX_CS2_N_MARK, EX_CS3_N_MARK,
229 EX_CS4_N_MARK, EX_CS5_N_MARK, BS_N_MARK, RD_N_MARK, RD_WR_N_MARK,
230 WE0_N_MARK, WE1_N_MARK, EX_WAIT0_MARK,
231 IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK, CS0_N_MARK,
232
233 VI0_CLK_MARK, VI0_CLKENB_MARK, VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
234 VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, VI0_D2_B2_C2_MARK,
235 VI0_D3_B3_C3_MARK, VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
236 VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK, VI0_D8_G0_Y0_MARK,
237 VI0_D9_G1_Y1_MARK, VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
238 VI0_FIELD_MARK,
239
240 VI1_CLK_MARK, VI1_CLKENB_MARK, VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
241 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, VI1_D2_B2_C2_MARK,
242 VI1_D3_B3_C3_MARK, VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
243 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, VI1_D8_G0_Y0_MARK,
244 VI1_D9_G1_Y1_MARK, VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
245 VI1_FIELD_MARK,
246
247 VI3_D10_Y2_MARK, VI3_FIELD_MARK,
248
249 VI4_CLK_MARK,
250
251 VI5_CLK_MARK, VI5_D9_Y1_MARK, VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
252 VI5_FIELD_MARK,
253
254 HRTS0_N_MARK, HCTS1_N_MARK, SCK0_MARK, CTS0_N_MARK, RTS0_N_MARK,
255 TX0_MARK, RX0_MARK, SCK1_MARK, CTS1_N_MARK, RTS1_N_MARK,
256 TX1_MARK, RX1_MARK, SCIF_CLK_MARK, CAN0_TX_MARK, CAN0_RX_MARK,
257 CAN_CLK_MARK, CAN1_TX_MARK, CAN1_RX_MARK,
258
259 SD0_CLK_MARK, SD0_CMD_MARK, SD0_DAT0_MARK, SD0_DAT1_MARK,
260 SD0_DAT2_MARK, SD0_DAT3_MARK, SD0_CD_MARK, SD0_WP_MARK,
261 ADICLK_MARK, ADICS_SAMP_MARK, ADIDATA_MARK, ADICHS0_MARK,
262 ADICHS1_MARK, ADICHS2_MARK, AVS1_MARK, AVS2_MARK,
263
264 /* IPSR0 */
265 DU0_DR0_DATA0_MARK, DU0_DR1_DATA1_MARK, DU0_DR2_Y4_DATA2_MARK,
266 DU0_DR3_Y5_DATA3_MARK, DU0_DR4_Y6_DATA4_MARK, DU0_DR5_Y7_DATA5_MARK,
267 DU0_DR6_Y8_DATA6_MARK, DU0_DR7_Y9_DATA7_MARK, DU0_DG0_DATA8_MARK,
268 DU0_DG1_DATA9_MARK, DU0_DG2_C6_DATA10_MARK, DU0_DG3_C7_DATA11_MARK,
269 DU0_DG4_Y0_DATA12_MARK, DU0_DG5_Y1_DATA13_MARK, DU0_DG6_Y2_DATA14_MARK,
270 DU0_DG7_Y3_DATA15_MARK, DU0_DB0_MARK, DU0_DB1_MARK,
271 DU0_DB2_C0_MARK, DU0_DB3_C1_MARK, DU0_DB4_C2_MARK, DU0_DB5_C3_MARK,
272 DU0_DB6_C4_MARK, DU0_DB7_C5_MARK,
273
274 /* IPSR1 */
275 DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
276 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, DU0_DISP_MARK, DU0_CDE_MARK,
277 DU1_DR2_Y4_DATA0_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR4_Y6_DATA2_MARK,
278 DU1_DR5_Y7_DATA3_MARK, DU1_DR6_DATA4_MARK, DU1_DR7_DATA5_MARK,
279 DU1_DG2_C6_DATA6_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG4_Y0_DATA8_MARK,
280 DU1_DG5_Y1_DATA9_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG7_Y3_DATA11_MARK,
281 A20_MARK, MOSI_IO0_MARK, A21_MARK, MISO_IO1_MARK, A22_MARK, IO2_MARK,
282 A23_MARK, IO3_MARK, A24_MARK, SPCLK_MARK, A25_MARK, SSL_MARK,
283
284 /* IPSR2 */
285 VI2_CLK_MARK, AVB_RX_CLK_MARK, VI2_CLKENB_MARK, AVB_RX_DV_MARK,
286 VI2_HSYNC_N_MARK, AVB_RXD0_MARK, VI2_VSYNC_N_MARK, AVB_RXD1_MARK,
287 VI2_D0_C0_MARK, AVB_RXD2_MARK, VI2_D1_C1_MARK, AVB_TX_CLK_MARK,
288 VI2_D2_C2_MARK, AVB_RXD4_MARK, VI2_D3_C3_MARK, AVB_RXD5_MARK,
289 VI2_D4_C4_MARK, AVB_RXD6_MARK, VI2_D5_C5_MARK, AVB_RXD7_MARK,
290 VI2_D6_C6_MARK, AVB_RX_ER_MARK, VI2_D7_C7_MARK, AVB_COL_MARK,
291 VI2_D8_Y0_MARK, AVB_RXD3_MARK, VI2_D9_Y1_MARK, AVB_TX_EN_MARK,
292 VI2_D10_Y2_MARK, AVB_TXD0_MARK,
293 VI2_D11_Y3_MARK, AVB_TXD1_MARK, VI2_FIELD_MARK, AVB_TXD2_MARK,
294
295 /* IPSR3 */
296 VI3_CLK_MARK, AVB_TXD3_MARK, VI3_CLKENB_MARK, AVB_TXD4_MARK,
297 VI3_HSYNC_N_MARK, AVB_TXD5_MARK, VI3_VSYNC_N_MARK, AVB_TXD6_MARK,
298 VI3_D0_C0_MARK, AVB_TXD7_MARK, VI3_D1_C1_MARK, AVB_TX_ER_MARK,
299 VI3_D2_C2_MARK, AVB_GTX_CLK_MARK, VI3_D3_C3_MARK, AVB_MDC_MARK,
300 VI3_D4_C4_MARK, AVB_MDIO_MARK, VI3_D5_C5_MARK, AVB_LINK_MARK,
301 VI3_D6_C6_MARK, AVB_MAGIC_MARK, VI3_D7_C7_MARK, AVB_PHY_INT_MARK,
302 VI3_D8_Y0_MARK, AVB_CRS_MARK, VI3_D9_Y1_MARK, AVB_GTXREFCLK_MARK,
303 VI3_D11_Y3_MARK, AVB_AVTP_MATCH_MARK,
304
305 /* IPSR4 */
306 VI4_CLKENB_MARK, VI0_D12_G4_Y4_MARK, VI4_HSYNC_N_MARK,
307 VI0_D13_G5_Y5_MARK, VI4_VSYNC_N_MARK, VI0_D14_G6_Y6_MARK,
308 RDR_CLKOUT_MARK, VI4_D0_C0_MARK, VI0_D15_G7_Y7_MARK, VI4_D1_C1_MARK,
309 VI0_D16_R0_MARK, VI1_D12_G4_Y4_MARK, VI4_D2_C2_MARK, VI0_D17_R1_MARK,
310 VI1_D13_G5_Y5_MARK, VI4_D3_C3_MARK, VI0_D18_R2_MARK, VI1_D14_G6_Y6_MARK,
311 VI4_D4_C4_MARK, VI0_D19_R3_MARK, VI1_D15_G7_Y7_MARK, VI4_D5_C5_MARK,
312 VI0_D20_R4_MARK, VI2_D12_Y4_MARK, VI4_D6_C6_MARK, VI0_D21_R5_MARK,
313 VI2_D13_Y5_MARK, VI4_D7_C7_MARK, VI0_D22_R6_MARK, VI2_D14_Y6_MARK,
314 VI4_D8_Y0_MARK, VI0_D23_R7_MARK, VI2_D15_Y7_MARK, VI4_D9_Y1_MARK,
315 VI3_D12_Y4_MARK, VI4_D10_Y2_MARK, VI3_D13_Y5_MARK, VI4_D11_Y3_MARK,
316 VI3_D14_Y6_MARK, VI4_FIELD_MARK, VI3_D15_Y7_MARK,
317
318 /* IPSR5 */
319 VI5_CLKENB_MARK, VI1_D12_G4_Y4_B_MARK, VI5_HSYNC_N_MARK,
320 VI1_D13_G5_Y5_B_MARK, VI5_VSYNC_N_MARK, VI1_D14_G6_Y6_B_MARK,
321 VI5_D0_C0_MARK, VI1_D15_G7_Y7_B_MARK, VI5_D1_C1_MARK, VI1_D16_R0_MARK,
322 VI5_D2_C2_MARK, VI1_D17_R1_MARK, VI5_D3_C3_MARK, VI1_D18_R2_MARK,
323 VI5_D4_C4_MARK, VI1_D19_R3_MARK, VI5_D5_C5_MARK, VI1_D20_R4_MARK,
324 VI5_D6_C6_MARK, VI1_D21_R5_MARK, VI5_D7_C7_MARK, VI1_D22_R6_MARK,
325 VI5_D8_Y0_MARK, VI1_D23_R7_MARK,
326
327 /* IPSR6 */
328 MSIOF0_SCK_MARK, HSCK0_MARK, MSIOF0_SYNC_MARK, HCTS0_N_MARK,
329 MSIOF0_TXD_MARK, HTX0_MARK, MSIOF0_RXD_MARK, HRX0_MARK,
330 MSIOF1_SCK_MARK, HSCK1_MARK, MSIOF1_SYNC_MARK, HRTS1_N_MARK,
331 MSIOF1_TXD_MARK, HTX1_MARK, MSIOF1_RXD_MARK, HRX1_MARK,
332 DRACK0_MARK, SCK2_MARK, DACK0_MARK, TX2_MARK, DREQ0_N_MARK,
333 RX2_MARK, DACK1_MARK, SCK3_MARK, TX3_MARK, DREQ1_N_MARK,
334 RX3_MARK,
335
336 /* IPSR7 */
337 PWM0_MARK, TCLK1_MARK, FSO_CFE_0_MARK, PWM1_MARK, TCLK2_MARK,
338 FSO_CFE_1_MARK, PWM2_MARK, TCLK3_MARK, FSO_TOE_MARK, PWM3_MARK,
339 PWM4_MARK, SSI_SCK34_MARK, TPU0TO0_MARK, SSI_WS34_MARK, TPU0TO1_MARK,
340 SSI_SDATA3_MARK, TPU0TO2_MARK, SSI_SCK4_MARK, TPU0TO3_MARK,
341 SSI_WS4_MARK, SSI_SDATA4_MARK, AUDIO_CLKOUT_MARK, AUDIO_CLKA_MARK,
342 AUDIO_CLKB_MARK,
343 PINMUX_MARK_END,
344};
345
346static const u16 pinmux_data[] = {
347 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
348
349 PINMUX_SINGLE(DU1_DB2_C0_DATA12),
350 PINMUX_SINGLE(DU1_DB3_C1_DATA13),
351 PINMUX_SINGLE(DU1_DB4_C2_DATA14),
352 PINMUX_SINGLE(DU1_DB5_C3_DATA15),
353 PINMUX_SINGLE(DU1_DB6_C4),
354 PINMUX_SINGLE(DU1_DB7_C5),
355 PINMUX_SINGLE(DU1_EXHSYNC_DU1_HSYNC),
356 PINMUX_SINGLE(DU1_EXVSYNC_DU1_VSYNC),
357 PINMUX_SINGLE(DU1_EXODDF_DU1_ODDF_DISP_CDE),
358 PINMUX_SINGLE(DU1_DISP),
359 PINMUX_SINGLE(DU1_CDE),
360 PINMUX_SINGLE(D0),
361 PINMUX_SINGLE(D1),
362 PINMUX_SINGLE(D2),
363 PINMUX_SINGLE(D3),
364 PINMUX_SINGLE(D4),
365 PINMUX_SINGLE(D5),
366 PINMUX_SINGLE(D6),
367 PINMUX_SINGLE(D7),
368 PINMUX_SINGLE(D8),
369 PINMUX_SINGLE(D9),
370 PINMUX_SINGLE(D10),
371 PINMUX_SINGLE(D11),
372 PINMUX_SINGLE(D12),
373 PINMUX_SINGLE(D13),
374 PINMUX_SINGLE(D14),
375 PINMUX_SINGLE(D15),
376 PINMUX_SINGLE(A0),
377 PINMUX_SINGLE(A1),
378 PINMUX_SINGLE(A2),
379 PINMUX_SINGLE(A3),
380 PINMUX_SINGLE(A4),
381 PINMUX_SINGLE(A5),
382 PINMUX_SINGLE(A6),
383 PINMUX_SINGLE(A7),
384 PINMUX_SINGLE(A8),
385 PINMUX_SINGLE(A9),
386 PINMUX_SINGLE(A10),
387 PINMUX_SINGLE(A11),
388 PINMUX_SINGLE(A12),
389 PINMUX_SINGLE(A13),
390 PINMUX_SINGLE(A14),
391 PINMUX_SINGLE(A15),
392 PINMUX_SINGLE(A16),
393 PINMUX_SINGLE(A17),
394 PINMUX_SINGLE(A18),
395 PINMUX_SINGLE(A19),
396 PINMUX_SINGLE(CS1_N_A26),
397 PINMUX_SINGLE(EX_CS0_N),
398 PINMUX_SINGLE(EX_CS1_N),
399 PINMUX_SINGLE(EX_CS2_N),
400 PINMUX_SINGLE(EX_CS3_N),
401 PINMUX_SINGLE(EX_CS4_N),
402 PINMUX_SINGLE(EX_CS5_N),
403 PINMUX_SINGLE(BS_N),
404 PINMUX_SINGLE(RD_N),
405 PINMUX_SINGLE(RD_WR_N),
406 PINMUX_SINGLE(WE0_N),
407 PINMUX_SINGLE(WE1_N),
408 PINMUX_SINGLE(EX_WAIT0),
409 PINMUX_SINGLE(IRQ0),
410 PINMUX_SINGLE(IRQ1),
411 PINMUX_SINGLE(IRQ2),
412 PINMUX_SINGLE(IRQ3),
413 PINMUX_SINGLE(CS0_N),
414 PINMUX_SINGLE(VI0_CLK),
415 PINMUX_SINGLE(VI0_CLKENB),
416 PINMUX_SINGLE(VI0_HSYNC_N),
417 PINMUX_SINGLE(VI0_VSYNC_N),
418 PINMUX_SINGLE(VI0_D0_B0_C0),
419 PINMUX_SINGLE(VI0_D1_B1_C1),
420 PINMUX_SINGLE(VI0_D2_B2_C2),
421 PINMUX_SINGLE(VI0_D3_B3_C3),
422 PINMUX_SINGLE(VI0_D4_B4_C4),
423 PINMUX_SINGLE(VI0_D5_B5_C5),
424 PINMUX_SINGLE(VI0_D6_B6_C6),
425 PINMUX_SINGLE(VI0_D7_B7_C7),
426 PINMUX_SINGLE(VI0_D8_G0_Y0),
427 PINMUX_SINGLE(VI0_D9_G1_Y1),
428 PINMUX_SINGLE(VI0_D10_G2_Y2),
429 PINMUX_SINGLE(VI0_D11_G3_Y3),
430 PINMUX_SINGLE(VI0_FIELD),
431 PINMUX_SINGLE(VI1_CLK),
432 PINMUX_SINGLE(VI1_CLKENB),
433 PINMUX_SINGLE(VI1_HSYNC_N),
434 PINMUX_SINGLE(VI1_VSYNC_N),
435 PINMUX_SINGLE(VI1_D0_B0_C0),
436 PINMUX_SINGLE(VI1_D1_B1_C1),
437 PINMUX_SINGLE(VI1_D2_B2_C2),
438 PINMUX_SINGLE(VI1_D3_B3_C3),
439 PINMUX_SINGLE(VI1_D4_B4_C4),
440 PINMUX_SINGLE(VI1_D5_B5_C5),
441 PINMUX_SINGLE(VI1_D6_B6_C6),
442 PINMUX_SINGLE(VI1_D7_B7_C7),
443 PINMUX_SINGLE(VI1_D8_G0_Y0),
444 PINMUX_SINGLE(VI1_D9_G1_Y1),
445 PINMUX_SINGLE(VI1_D10_G2_Y2),
446 PINMUX_SINGLE(VI1_D11_G3_Y3),
447 PINMUX_SINGLE(VI1_FIELD),
448 PINMUX_SINGLE(VI3_D10_Y2),
449 PINMUX_SINGLE(VI3_FIELD),
450 PINMUX_SINGLE(VI4_CLK),
451 PINMUX_SINGLE(VI5_CLK),
452 PINMUX_SINGLE(VI5_D9_Y1),
453 PINMUX_SINGLE(VI5_D10_Y2),
454 PINMUX_SINGLE(VI5_D11_Y3),
455 PINMUX_SINGLE(VI5_FIELD),
456 PINMUX_SINGLE(HRTS0_N),
457 PINMUX_SINGLE(HCTS1_N),
458 PINMUX_SINGLE(SCK0),
459 PINMUX_SINGLE(CTS0_N),
460 PINMUX_SINGLE(RTS0_N),
461 PINMUX_SINGLE(TX0),
462 PINMUX_SINGLE(RX0),
463 PINMUX_SINGLE(SCK1),
464 PINMUX_SINGLE(CTS1_N),
465 PINMUX_SINGLE(RTS1_N),
466 PINMUX_SINGLE(TX1),
467 PINMUX_SINGLE(RX1),
468 PINMUX_SINGLE(SCIF_CLK),
469 PINMUX_SINGLE(CAN0_TX),
470 PINMUX_SINGLE(CAN0_RX),
471 PINMUX_SINGLE(CAN_CLK),
472 PINMUX_SINGLE(CAN1_TX),
473 PINMUX_SINGLE(CAN1_RX),
474 PINMUX_SINGLE(SD0_CLK),
475 PINMUX_SINGLE(SD0_CMD),
476 PINMUX_SINGLE(SD0_DAT0),
477 PINMUX_SINGLE(SD0_DAT1),
478 PINMUX_SINGLE(SD0_DAT2),
479 PINMUX_SINGLE(SD0_DAT3),
480 PINMUX_SINGLE(SD0_CD),
481 PINMUX_SINGLE(SD0_WP),
482 PINMUX_SINGLE(ADICLK),
483 PINMUX_SINGLE(ADICS_SAMP),
484 PINMUX_SINGLE(ADIDATA),
485 PINMUX_SINGLE(ADICHS0),
486 PINMUX_SINGLE(ADICHS1),
487 PINMUX_SINGLE(ADICHS2),
488 PINMUX_SINGLE(AVS1),
489 PINMUX_SINGLE(AVS2),
490
491 /* IPSR0 */
492 PINMUX_IPSR_GPSR(IP0_0, DU0_DR0_DATA0),
493 PINMUX_IPSR_GPSR(IP0_1, DU0_DR1_DATA1),
494 PINMUX_IPSR_GPSR(IP0_2, DU0_DR2_Y4_DATA2),
495 PINMUX_IPSR_GPSR(IP0_3, DU0_DR3_Y5_DATA3),
496 PINMUX_IPSR_GPSR(IP0_4, DU0_DR4_Y6_DATA4),
497 PINMUX_IPSR_GPSR(IP0_5, DU0_DR5_Y7_DATA5),
498 PINMUX_IPSR_GPSR(IP0_6, DU0_DR6_Y8_DATA6),
499 PINMUX_IPSR_GPSR(IP0_7, DU0_DR7_Y9_DATA7),
500 PINMUX_IPSR_GPSR(IP0_8, DU0_DG0_DATA8),
501 PINMUX_IPSR_GPSR(IP0_9, DU0_DG1_DATA9),
502 PINMUX_IPSR_GPSR(IP0_10, DU0_DG2_C6_DATA10),
503 PINMUX_IPSR_GPSR(IP0_11, DU0_DG3_C7_DATA11),
504 PINMUX_IPSR_GPSR(IP0_12, DU0_DG4_Y0_DATA12),
505 PINMUX_IPSR_GPSR(IP0_13, DU0_DG5_Y1_DATA13),
506 PINMUX_IPSR_GPSR(IP0_14, DU0_DG6_Y2_DATA14),
507 PINMUX_IPSR_GPSR(IP0_15, DU0_DG7_Y3_DATA15),
508 PINMUX_IPSR_GPSR(IP0_16, DU0_DB0),
509 PINMUX_IPSR_GPSR(IP0_17, DU0_DB1),
510 PINMUX_IPSR_GPSR(IP0_18, DU0_DB2_C0),
511 PINMUX_IPSR_GPSR(IP0_19, DU0_DB3_C1),
512 PINMUX_IPSR_GPSR(IP0_20, DU0_DB4_C2),
513 PINMUX_IPSR_GPSR(IP0_21, DU0_DB5_C3),
514 PINMUX_IPSR_GPSR(IP0_22, DU0_DB6_C4),
515 PINMUX_IPSR_GPSR(IP0_23, DU0_DB7_C5),
516
517 /* IPSR1 */
518 PINMUX_IPSR_GPSR(IP1_0, DU0_EXHSYNC_DU0_HSYNC),
519 PINMUX_IPSR_GPSR(IP1_1, DU0_EXVSYNC_DU0_VSYNC),
520 PINMUX_IPSR_GPSR(IP1_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
521 PINMUX_IPSR_GPSR(IP1_3, DU0_DISP),
522 PINMUX_IPSR_GPSR(IP1_4, DU0_CDE),
523 PINMUX_IPSR_GPSR(IP1_5, DU1_DR2_Y4_DATA0),
524 PINMUX_IPSR_GPSR(IP1_6, DU1_DR3_Y5_DATA1),
525 PINMUX_IPSR_GPSR(IP1_7, DU1_DR4_Y6_DATA2),
526 PINMUX_IPSR_GPSR(IP1_8, DU1_DR5_Y7_DATA3),
527 PINMUX_IPSR_GPSR(IP1_9, DU1_DR6_DATA4),
528 PINMUX_IPSR_GPSR(IP1_10, DU1_DR7_DATA5),
529 PINMUX_IPSR_GPSR(IP1_11, DU1_DG2_C6_DATA6),
530 PINMUX_IPSR_GPSR(IP1_12, DU1_DG3_C7_DATA7),
531 PINMUX_IPSR_GPSR(IP1_13, DU1_DG4_Y0_DATA8),
532 PINMUX_IPSR_GPSR(IP1_14, DU1_DG5_Y1_DATA9),
533 PINMUX_IPSR_GPSR(IP1_15, DU1_DG6_Y2_DATA10),
534 PINMUX_IPSR_GPSR(IP1_16, DU1_DG7_Y3_DATA11),
535 PINMUX_IPSR_GPSR(IP1_17, A20),
536 PINMUX_IPSR_GPSR(IP1_17, MOSI_IO0),
537 PINMUX_IPSR_GPSR(IP1_18, A21),
538 PINMUX_IPSR_GPSR(IP1_18, MISO_IO1),
539 PINMUX_IPSR_GPSR(IP1_19, A22),
540 PINMUX_IPSR_GPSR(IP1_19, IO2),
541 PINMUX_IPSR_GPSR(IP1_20, A23),
542 PINMUX_IPSR_GPSR(IP1_20, IO3),
543 PINMUX_IPSR_GPSR(IP1_21, A24),
544 PINMUX_IPSR_GPSR(IP1_21, SPCLK),
545 PINMUX_IPSR_GPSR(IP1_22, A25),
546 PINMUX_IPSR_GPSR(IP1_22, SSL),
547
548 /* IPSR2 */
549 PINMUX_IPSR_GPSR(IP2_0, VI2_CLK),
550 PINMUX_IPSR_GPSR(IP2_0, AVB_RX_CLK),
551 PINMUX_IPSR_GPSR(IP2_1, VI2_CLKENB),
552 PINMUX_IPSR_GPSR(IP2_1, AVB_RX_DV),
553 PINMUX_IPSR_GPSR(IP2_2, VI2_HSYNC_N),
554 PINMUX_IPSR_GPSR(IP2_2, AVB_RXD0),
555 PINMUX_IPSR_GPSR(IP2_3, VI2_VSYNC_N),
556 PINMUX_IPSR_GPSR(IP2_3, AVB_RXD1),
557 PINMUX_IPSR_GPSR(IP2_4, VI2_D0_C0),
558 PINMUX_IPSR_GPSR(IP2_4, AVB_RXD2),
559 PINMUX_IPSR_GPSR(IP2_5, VI2_D1_C1),
560 PINMUX_IPSR_GPSR(IP2_5, AVB_RXD3),
561 PINMUX_IPSR_GPSR(IP2_6, VI2_D2_C2),
562 PINMUX_IPSR_GPSR(IP2_6, AVB_RXD4),
563 PINMUX_IPSR_GPSR(IP2_7, VI2_D3_C3),
564 PINMUX_IPSR_GPSR(IP2_7, AVB_RXD5),
565 PINMUX_IPSR_GPSR(IP2_8, VI2_D4_C4),
566 PINMUX_IPSR_GPSR(IP2_8, AVB_RXD6),
567 PINMUX_IPSR_GPSR(IP2_9, VI2_D5_C5),
568 PINMUX_IPSR_GPSR(IP2_9, AVB_RXD7),
569 PINMUX_IPSR_GPSR(IP2_10, VI2_D6_C6),
570 PINMUX_IPSR_GPSR(IP2_10, AVB_RX_ER),
571 PINMUX_IPSR_GPSR(IP2_11, VI2_D7_C7),
572 PINMUX_IPSR_GPSR(IP2_11, AVB_COL),
573 PINMUX_IPSR_GPSR(IP2_12, VI2_D8_Y0),
574 PINMUX_IPSR_GPSR(IP2_12, AVB_TXD3),
575 PINMUX_IPSR_GPSR(IP2_13, VI2_D9_Y1),
576 PINMUX_IPSR_GPSR(IP2_13, AVB_TX_EN),
577 PINMUX_IPSR_GPSR(IP2_14, VI2_D10_Y2),
578 PINMUX_IPSR_GPSR(IP2_14, AVB_TXD0),
579 PINMUX_IPSR_GPSR(IP2_15, VI2_D11_Y3),
580 PINMUX_IPSR_GPSR(IP2_15, AVB_TXD1),
581 PINMUX_IPSR_GPSR(IP2_16, VI2_FIELD),
582 PINMUX_IPSR_GPSR(IP2_16, AVB_TXD2),
583
584 /* IPSR3 */
585 PINMUX_IPSR_GPSR(IP3_0, VI3_CLK),
586 PINMUX_IPSR_GPSR(IP3_0, AVB_TX_CLK),
587 PINMUX_IPSR_GPSR(IP3_1, VI3_CLKENB),
588 PINMUX_IPSR_GPSR(IP3_1, AVB_TXD4),
589 PINMUX_IPSR_GPSR(IP3_2, VI3_HSYNC_N),
590 PINMUX_IPSR_GPSR(IP3_2, AVB_TXD5),
591 PINMUX_IPSR_GPSR(IP3_3, VI3_VSYNC_N),
592 PINMUX_IPSR_GPSR(IP3_3, AVB_TXD6),
593 PINMUX_IPSR_GPSR(IP3_4, VI3_D0_C0),
594 PINMUX_IPSR_GPSR(IP3_4, AVB_TXD7),
595 PINMUX_IPSR_GPSR(IP3_5, VI3_D1_C1),
596 PINMUX_IPSR_GPSR(IP3_5, AVB_TX_ER),
597 PINMUX_IPSR_GPSR(IP3_6, VI3_D2_C2),
598 PINMUX_IPSR_GPSR(IP3_6, AVB_GTX_CLK),
599 PINMUX_IPSR_GPSR(IP3_7, VI3_D3_C3),
600 PINMUX_IPSR_GPSR(IP3_7, AVB_MDC),
601 PINMUX_IPSR_GPSR(IP3_8, VI3_D4_C4),
602 PINMUX_IPSR_GPSR(IP3_8, AVB_MDIO),
603 PINMUX_IPSR_GPSR(IP3_9, VI3_D5_C5),
604 PINMUX_IPSR_GPSR(IP3_9, AVB_LINK),
605 PINMUX_IPSR_GPSR(IP3_10, VI3_D6_C6),
606 PINMUX_IPSR_GPSR(IP3_10, AVB_MAGIC),
607 PINMUX_IPSR_GPSR(IP3_11, VI3_D7_C7),
608 PINMUX_IPSR_GPSR(IP3_11, AVB_PHY_INT),
609 PINMUX_IPSR_GPSR(IP3_12, VI3_D8_Y0),
610 PINMUX_IPSR_GPSR(IP3_12, AVB_CRS),
611 PINMUX_IPSR_GPSR(IP3_13, VI3_D9_Y1),
612 PINMUX_IPSR_GPSR(IP3_13, AVB_GTXREFCLK),
613 PINMUX_IPSR_GPSR(IP3_14, VI3_D11_Y3),
614 PINMUX_IPSR_GPSR(IP3_14, AVB_AVTP_MATCH),
615
616 /* IPSR4 */
617 PINMUX_IPSR_GPSR(IP4_0, VI4_CLKENB),
618 PINMUX_IPSR_GPSR(IP4_0, VI0_D12_G4_Y4),
619 PINMUX_IPSR_GPSR(IP4_1, VI4_HSYNC_N),
620 PINMUX_IPSR_GPSR(IP4_1, VI0_D13_G5_Y5),
621 PINMUX_IPSR_GPSR(IP4_3_2, VI4_VSYNC_N),
622 PINMUX_IPSR_GPSR(IP4_3_2, VI0_D14_G6_Y6),
623 PINMUX_IPSR_GPSR(IP4_4, VI4_D0_C0),
624 PINMUX_IPSR_GPSR(IP4_4, VI0_D15_G7_Y7),
625 PINMUX_IPSR_GPSR(IP4_6_5, VI4_D1_C1),
626 PINMUX_IPSR_GPSR(IP4_6_5, VI0_D16_R0),
627 PINMUX_IPSR_MSEL(IP4_6_5, VI1_D12_G4_Y4, SEL_VI1_0),
628 PINMUX_IPSR_GPSR(IP4_8_7, VI4_D2_C2),
629 PINMUX_IPSR_GPSR(IP4_8_7, VI0_D17_R1),
630 PINMUX_IPSR_MSEL(IP4_8_7, VI1_D13_G5_Y5, SEL_VI1_0),
631 PINMUX_IPSR_GPSR(IP4_10_9, VI4_D3_C3),
632 PINMUX_IPSR_GPSR(IP4_10_9, VI0_D18_R2),
633 PINMUX_IPSR_MSEL(IP4_10_9, VI1_D14_G6_Y6, SEL_VI1_0),
634 PINMUX_IPSR_GPSR(IP4_12_11, VI4_D4_C4),
635 PINMUX_IPSR_GPSR(IP4_12_11, VI0_D19_R3),
636 PINMUX_IPSR_MSEL(IP4_12_11, VI1_D15_G7_Y7, SEL_VI1_0),
637 PINMUX_IPSR_GPSR(IP4_14_13, VI4_D5_C5),
638 PINMUX_IPSR_GPSR(IP4_14_13, VI0_D20_R4),
639 PINMUX_IPSR_GPSR(IP4_14_13, VI2_D12_Y4),
640 PINMUX_IPSR_GPSR(IP4_16_15, VI4_D6_C6),
641 PINMUX_IPSR_GPSR(IP4_16_15, VI0_D21_R5),
642 PINMUX_IPSR_GPSR(IP4_16_15, VI2_D13_Y5),
643 PINMUX_IPSR_GPSR(IP4_18_17, VI4_D7_C7),
644 PINMUX_IPSR_GPSR(IP4_18_17, VI0_D22_R6),
645 PINMUX_IPSR_GPSR(IP4_18_17, VI2_D14_Y6),
646 PINMUX_IPSR_GPSR(IP4_20_19, VI4_D8_Y0),
647 PINMUX_IPSR_GPSR(IP4_20_19, VI0_D23_R7),
648 PINMUX_IPSR_GPSR(IP4_20_19, VI2_D15_Y7),
649 PINMUX_IPSR_GPSR(IP4_21, VI4_D9_Y1),
650 PINMUX_IPSR_GPSR(IP4_21, VI3_D12_Y4),
651 PINMUX_IPSR_GPSR(IP4_22, VI4_D10_Y2),
652 PINMUX_IPSR_GPSR(IP4_22, VI3_D13_Y5),
653 PINMUX_IPSR_GPSR(IP4_23, VI4_D11_Y3),
654 PINMUX_IPSR_GPSR(IP4_23, VI3_D14_Y6),
655 PINMUX_IPSR_GPSR(IP4_24, VI4_FIELD),
656 PINMUX_IPSR_GPSR(IP4_24, VI3_D15_Y7),
657
658 /* IPSR5 */
659 PINMUX_IPSR_GPSR(IP5_0, VI5_CLKENB),
660 PINMUX_IPSR_MSEL(IP5_0, VI1_D12_G4_Y4_B, SEL_VI1_1),
661 PINMUX_IPSR_GPSR(IP5_1, VI5_HSYNC_N),
662 PINMUX_IPSR_MSEL(IP5_1, VI1_D13_G5_Y5_B, SEL_VI1_1),
663 PINMUX_IPSR_GPSR(IP5_2, VI5_VSYNC_N),
664 PINMUX_IPSR_MSEL(IP5_2, VI1_D14_G6_Y6_B, SEL_VI1_1),
665 PINMUX_IPSR_GPSR(IP5_3, VI5_D0_C0),
666 PINMUX_IPSR_MSEL(IP5_3, VI1_D15_G7_Y7_B, SEL_VI1_1),
667 PINMUX_IPSR_GPSR(IP5_4, VI5_D1_C1),
668 PINMUX_IPSR_GPSR(IP5_4, VI1_D16_R0),
669 PINMUX_IPSR_GPSR(IP5_5, VI5_D2_C2),
670 PINMUX_IPSR_GPSR(IP5_5, VI1_D17_R1),
671 PINMUX_IPSR_GPSR(IP5_6, VI5_D3_C3),
672 PINMUX_IPSR_GPSR(IP5_6, VI1_D18_R2),
673 PINMUX_IPSR_GPSR(IP5_7, VI5_D4_C4),
674 PINMUX_IPSR_GPSR(IP5_7, VI1_D19_R3),
675 PINMUX_IPSR_GPSR(IP5_8, VI5_D5_C5),
676 PINMUX_IPSR_GPSR(IP5_8, VI1_D20_R4),
677 PINMUX_IPSR_GPSR(IP5_9, VI5_D6_C6),
678 PINMUX_IPSR_GPSR(IP5_9, VI1_D21_R5),
679 PINMUX_IPSR_GPSR(IP5_10, VI5_D7_C7),
680 PINMUX_IPSR_GPSR(IP5_10, VI1_D22_R6),
681 PINMUX_IPSR_GPSR(IP5_11, VI5_D8_Y0),
682 PINMUX_IPSR_GPSR(IP5_11, VI1_D23_R7),
683
684 /* IPSR6 */
685 PINMUX_IPSR_GPSR(IP6_0, MSIOF0_SCK),
686 PINMUX_IPSR_GPSR(IP6_0, HSCK0),
687 PINMUX_IPSR_GPSR(IP6_1, MSIOF0_SYNC),
688 PINMUX_IPSR_GPSR(IP6_1, HCTS0_N),
689 PINMUX_IPSR_GPSR(IP6_2, MSIOF0_TXD),
690 PINMUX_IPSR_GPSR(IP6_2, HTX0),
691 PINMUX_IPSR_GPSR(IP6_3, MSIOF0_RXD),
692 PINMUX_IPSR_GPSR(IP6_3, HRX0),
693 PINMUX_IPSR_GPSR(IP6_4, MSIOF1_SCK),
694 PINMUX_IPSR_GPSR(IP6_4, HSCK1),
695 PINMUX_IPSR_GPSR(IP6_5, MSIOF1_SYNC),
696 PINMUX_IPSR_GPSR(IP6_5, HRTS1_N),
697 PINMUX_IPSR_GPSR(IP6_6, MSIOF1_TXD),
698 PINMUX_IPSR_GPSR(IP6_6, HTX1),
699 PINMUX_IPSR_GPSR(IP6_7, MSIOF1_RXD),
700 PINMUX_IPSR_GPSR(IP6_7, HRX1),
701 PINMUX_IPSR_GPSR(IP6_9_8, DRACK0),
702 PINMUX_IPSR_GPSR(IP6_9_8, SCK2),
703 PINMUX_IPSR_GPSR(IP6_11_10, DACK0),
704 PINMUX_IPSR_GPSR(IP6_11_10, TX2),
705 PINMUX_IPSR_GPSR(IP6_13_12, DREQ0_N),
706 PINMUX_IPSR_GPSR(IP6_13_12, RX2),
707 PINMUX_IPSR_GPSR(IP6_15_14, DACK1),
708 PINMUX_IPSR_GPSR(IP6_15_14, SCK3),
709 PINMUX_IPSR_GPSR(IP6_16, TX3),
710 PINMUX_IPSR_GPSR(IP6_18_17, DREQ1_N),
711 PINMUX_IPSR_GPSR(IP6_18_17, RX3),
712
713 /* IPSR7 */
714 PINMUX_IPSR_GPSR(IP7_1_0, PWM0),
715 PINMUX_IPSR_GPSR(IP7_1_0, TCLK1),
716 PINMUX_IPSR_GPSR(IP7_1_0, FSO_CFE_0),
717 PINMUX_IPSR_GPSR(IP7_3_2, PWM1),
718 PINMUX_IPSR_GPSR(IP7_3_2, TCLK2),
719 PINMUX_IPSR_GPSR(IP7_3_2, FSO_CFE_1),
720 PINMUX_IPSR_GPSR(IP7_5_4, PWM2),
721 PINMUX_IPSR_GPSR(IP7_5_4, TCLK3),
722 PINMUX_IPSR_GPSR(IP7_5_4, FSO_TOE),
723 PINMUX_IPSR_GPSR(IP7_6, PWM3),
724 PINMUX_IPSR_GPSR(IP7_7, PWM4),
725 PINMUX_IPSR_GPSR(IP7_9_8, SSI_SCK34),
726 PINMUX_IPSR_GPSR(IP7_9_8, TPU0TO0),
727 PINMUX_IPSR_GPSR(IP7_11_10, SSI_WS34),
728 PINMUX_IPSR_GPSR(IP7_11_10, TPU0TO1),
729 PINMUX_IPSR_GPSR(IP7_13_12, SSI_SDATA3),
730 PINMUX_IPSR_GPSR(IP7_13_12, TPU0TO2),
731 PINMUX_IPSR_GPSR(IP7_15_14, SSI_SCK4),
732 PINMUX_IPSR_GPSR(IP7_15_14, TPU0TO3),
733 PINMUX_IPSR_GPSR(IP7_16, SSI_WS4),
734 PINMUX_IPSR_GPSR(IP7_17, SSI_SDATA4),
735 PINMUX_IPSR_GPSR(IP7_18, AUDIO_CLKOUT),
736 PINMUX_IPSR_GPSR(IP7_19, AUDIO_CLKA),
737 PINMUX_IPSR_GPSR(IP7_20, AUDIO_CLKB),
738};
739
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]740/*
741 * Pins not associated with a GPIO port.
742 */
743enum {
744 GP_ASSIGN_LAST(),
745 NOGP_ALL(),
746};
747
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]748static const struct sh_pfc_pin pinmux_pins[] = {
749 PINMUX_GPIO_GP_ALL(),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]750 PINMUX_NOGP_ALL(),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]751};
752
753/* - AVB -------------------------------------------------------------------- */
754static const unsigned int avb_link_pins[] = {
755 RCAR_GP_PIN(7, 9),
756};
757static const unsigned int avb_link_mux[] = {
758 AVB_LINK_MARK,
759};
760static const unsigned int avb_magic_pins[] = {
761 RCAR_GP_PIN(7, 10),
762};
763static const unsigned int avb_magic_mux[] = {
764 AVB_MAGIC_MARK,
765};
766static const unsigned int avb_phy_int_pins[] = {
767 RCAR_GP_PIN(7, 11),
768};
769static const unsigned int avb_phy_int_mux[] = {
770 AVB_PHY_INT_MARK,
771};
772static const unsigned int avb_mdio_pins[] = {
773 RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8),
774};
775static const unsigned int avb_mdio_mux[] = {
776 AVB_MDC_MARK, AVB_MDIO_MARK,
777};
778static const unsigned int avb_mii_pins[] = {
779 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
780 RCAR_GP_PIN(6, 12),
781
782 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
783 RCAR_GP_PIN(6, 5),
784
785 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
786 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5),
787 RCAR_GP_PIN(7, 0), RCAR_GP_PIN(6, 11),
788};
789static const unsigned int avb_mii_mux[] = {
790 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
791 AVB_TXD3_MARK,
792
793 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
794 AVB_RXD3_MARK,
795
796 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
797 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
798 AVB_TX_CLK_MARK, AVB_COL_MARK,
799};
800static const unsigned int avb_gmii_pins[] = {
801 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
802 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 2),
803 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
804
805 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
806 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
807 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
808
809 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
810 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 13),
811 RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 0),
812 RCAR_GP_PIN(6, 11),
813};
814static const unsigned int avb_gmii_mux[] = {
815 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
816 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
817 AVB_TXD6_MARK, AVB_TXD7_MARK,
818
819 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
820 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
821 AVB_RXD6_MARK, AVB_RXD7_MARK,
822
823 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
824 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
825 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
826 AVB_COL_MARK,
827};
828static const unsigned int avb_avtp_match_pins[] = {
829 RCAR_GP_PIN(7, 15),
830};
831static const unsigned int avb_avtp_match_mux[] = {
832 AVB_AVTP_MATCH_MARK,
833};
Marek Vasut47ef1c82024-12-23 14:34:08 +0100[diff] [blame]834
835#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]836/* - CAN -------------------------------------------------------------------- */
837static const unsigned int can0_data_pins[] = {
838 /* TX, RX */
839 RCAR_GP_PIN(10, 27), RCAR_GP_PIN(10, 28),
840};
841static const unsigned int can0_data_mux[] = {
842 CAN0_TX_MARK, CAN0_RX_MARK,
843};
844static const unsigned int can1_data_pins[] = {
845 /* TX, RX */
846 RCAR_GP_PIN(10, 30), RCAR_GP_PIN(10, 31),
847};
848static const unsigned int can1_data_mux[] = {
849 CAN1_TX_MARK, CAN1_RX_MARK,
850};
851static const unsigned int can_clk_pins[] = {
852 /* CAN_CLK */
853 RCAR_GP_PIN(10, 29),
854};
855static const unsigned int can_clk_mux[] = {
856 CAN_CLK_MARK,
857};
858/* - DU --------------------------------------------------------------------- */
859static const unsigned int du0_rgb666_pins[] = {
860 /* R[7:2], G[7:2], B[7:2] */
861 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
862 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
863 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
864 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
865 RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
866 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
867};
868static const unsigned int du0_rgb666_mux[] = {
869 DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
870 DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
871 DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
872 DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
873 DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
874 DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
875};
876static const unsigned int du0_rgb888_pins[] = {
877 /* R[7:0], G[7:0], B[7:0] */
878 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
879 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
880 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
881 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
882 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
883 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
884 RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
885 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
886 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
887};
888static const unsigned int du0_rgb888_mux[] = {
889 DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
890 DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
891 DU0_DR1_DATA1_MARK, DU0_DR0_DATA0_MARK,
892 DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
893 DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
894 DU0_DG1_DATA9_MARK, DU0_DG0_DATA8_MARK,
895 DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
896 DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
897 DU0_DB1_MARK, DU0_DB0_MARK,
898};
899static const unsigned int du0_sync_pins[] = {
900 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
901 RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 24),
902};
903static const unsigned int du0_sync_mux[] = {
904 DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
905};
906static const unsigned int du0_oddf_pins[] = {
907 /* EXODDF/ODDF/DISP/CDE */
908 RCAR_GP_PIN(0, 26),
909};
910static const unsigned int du0_oddf_mux[] = {
911 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
912};
913static const unsigned int du0_disp_pins[] = {
914 /* DISP */
915 RCAR_GP_PIN(0, 27),
916};
917static const unsigned int du0_disp_mux[] = {
918 DU0_DISP_MARK,
919};
920static const unsigned int du0_cde_pins[] = {
921 /* CDE */
922 RCAR_GP_PIN(0, 28),
923};
924static const unsigned int du0_cde_mux[] = {
925 DU0_CDE_MARK,
926};
927static const unsigned int du1_rgb666_pins[] = {
928 /* R[7:2], G[7:2], B[7:2] */
929 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
930 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
931 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
932 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
933 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
934 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
935};
936static const unsigned int du1_rgb666_mux[] = {
937 DU1_DR7_DATA5_MARK, DU1_DR6_DATA4_MARK, DU1_DR5_Y7_DATA3_MARK,
938 DU1_DR4_Y6_DATA2_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR2_Y4_DATA0_MARK,
939 DU1_DG7_Y3_DATA11_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG5_Y1_DATA9_MARK,
940 DU1_DG4_Y0_DATA8_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG2_C6_DATA6_MARK,
941 DU1_DB7_C5_MARK, DU1_DB6_C4_MARK, DU1_DB5_C3_DATA15_MARK,
942 DU1_DB4_C2_DATA14_MARK, DU1_DB3_C1_DATA13_MARK, DU1_DB2_C0_DATA12_MARK,
943};
944static const unsigned int du1_sync_pins[] = {
945 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
946 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
947};
948static const unsigned int du1_sync_mux[] = {
949 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
950};
951static const unsigned int du1_oddf_pins[] = {
952 /* EXODDF/ODDF/DISP/CDE */
953 RCAR_GP_PIN(1, 20),
954};
955static const unsigned int du1_oddf_mux[] = {
956 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
957};
958static const unsigned int du1_disp_pins[] = {
959 /* DISP */
960 RCAR_GP_PIN(1, 21),
961};
962static const unsigned int du1_disp_mux[] = {
963 DU1_DISP_MARK,
964};
965static const unsigned int du1_cde_pins[] = {
966 /* CDE */
967 RCAR_GP_PIN(1, 22),
968};
969static const unsigned int du1_cde_mux[] = {
970 DU1_CDE_MARK,
971};
972/* - INTC ------------------------------------------------------------------- */
973static const unsigned int intc_irq0_pins[] = {
974 /* IRQ0 */
975 RCAR_GP_PIN(3, 19),
976};
977static const unsigned int intc_irq0_mux[] = {
978 IRQ0_MARK,
979};
980static const unsigned int intc_irq1_pins[] = {
981 /* IRQ1 */
982 RCAR_GP_PIN(3, 20),
983};
984static const unsigned int intc_irq1_mux[] = {
985 IRQ1_MARK,
986};
987static const unsigned int intc_irq2_pins[] = {
988 /* IRQ2 */
989 RCAR_GP_PIN(3, 21),
990};
991static const unsigned int intc_irq2_mux[] = {
992 IRQ2_MARK,
993};
994static const unsigned int intc_irq3_pins[] = {
995 /* IRQ3 */
996 RCAR_GP_PIN(3, 22),
997};
998static const unsigned int intc_irq3_mux[] = {
999 IRQ3_MARK,
1000};
Marek Vasut47ef1c82024-12-23 14:34:08 +0100[diff] [blame]1001#endif
1002
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1003/* - LBSC ------------------------------------------------------------------- */
1004static const unsigned int lbsc_cs0_pins[] = {
1005 /* CS0# */
1006 RCAR_GP_PIN(3, 27),
1007};
1008static const unsigned int lbsc_cs0_mux[] = {
1009 CS0_N_MARK,
1010};
1011static const unsigned int lbsc_cs1_pins[] = {
1012 /* CS1#_A26 */
1013 RCAR_GP_PIN(3, 6),
1014};
1015static const unsigned int lbsc_cs1_mux[] = {
1016 CS1_N_A26_MARK,
1017};
1018static const unsigned int lbsc_ex_cs0_pins[] = {
1019 /* EX_CS0# */
1020 RCAR_GP_PIN(3, 7),
1021};
1022static const unsigned int lbsc_ex_cs0_mux[] = {
1023 EX_CS0_N_MARK,
1024};
1025static const unsigned int lbsc_ex_cs1_pins[] = {
1026 /* EX_CS1# */
1027 RCAR_GP_PIN(3, 8),
1028};
1029static const unsigned int lbsc_ex_cs1_mux[] = {
1030 EX_CS1_N_MARK,
1031};
1032static const unsigned int lbsc_ex_cs2_pins[] = {
1033 /* EX_CS2# */
1034 RCAR_GP_PIN(3, 9),
1035};
1036static const unsigned int lbsc_ex_cs2_mux[] = {
1037 EX_CS2_N_MARK,
1038};
1039static const unsigned int lbsc_ex_cs3_pins[] = {
1040 /* EX_CS3# */
1041 RCAR_GP_PIN(3, 10),
1042};
1043static const unsigned int lbsc_ex_cs3_mux[] = {
1044 EX_CS3_N_MARK,
1045};
1046static const unsigned int lbsc_ex_cs4_pins[] = {
1047 /* EX_CS4# */
1048 RCAR_GP_PIN(3, 11),
1049};
1050static const unsigned int lbsc_ex_cs4_mux[] = {
1051 EX_CS4_N_MARK,
1052};
1053static const unsigned int lbsc_ex_cs5_pins[] = {
1054 /* EX_CS5# */
1055 RCAR_GP_PIN(3, 12),
1056};
1057static const unsigned int lbsc_ex_cs5_mux[] = {
1058 EX_CS5_N_MARK,
1059};
Marek Vasut47ef1c82024-12-23 14:34:08 +0100[diff] [blame]1060
1061#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1062/* - MSIOF0 ----------------------------------------------------------------- */
1063static const unsigned int msiof0_clk_pins[] = {
1064 /* SCK */
1065 RCAR_GP_PIN(10, 0),
1066};
1067static const unsigned int msiof0_clk_mux[] = {
1068 MSIOF0_SCK_MARK,
1069};
1070static const unsigned int msiof0_sync_pins[] = {
1071 /* SYNC */
1072 RCAR_GP_PIN(10, 1),
1073};
1074static const unsigned int msiof0_sync_mux[] = {
1075 MSIOF0_SYNC_MARK,
1076};
1077static const unsigned int msiof0_rx_pins[] = {
1078 /* RXD */
1079 RCAR_GP_PIN(10, 4),
1080};
1081static const unsigned int msiof0_rx_mux[] = {
1082 MSIOF0_RXD_MARK,
1083};
1084static const unsigned int msiof0_tx_pins[] = {
1085 /* TXD */
1086 RCAR_GP_PIN(10, 3),
1087};
1088static const unsigned int msiof0_tx_mux[] = {
1089 MSIOF0_TXD_MARK,
1090};
1091/* - MSIOF1 ----------------------------------------------------------------- */
1092static const unsigned int msiof1_clk_pins[] = {
1093 /* SCK */
1094 RCAR_GP_PIN(10, 5),
1095};
1096static const unsigned int msiof1_clk_mux[] = {
1097 MSIOF1_SCK_MARK,
1098};
1099static const unsigned int msiof1_sync_pins[] = {
1100 /* SYNC */
1101 RCAR_GP_PIN(10, 6),
1102};
1103static const unsigned int msiof1_sync_mux[] = {
1104 MSIOF1_SYNC_MARK,
1105};
1106static const unsigned int msiof1_rx_pins[] = {
1107 /* RXD */
1108 RCAR_GP_PIN(10, 9),
1109};
1110static const unsigned int msiof1_rx_mux[] = {
1111 MSIOF1_RXD_MARK,
1112};
1113static const unsigned int msiof1_tx_pins[] = {
1114 /* TXD */
1115 RCAR_GP_PIN(10, 8),
1116};
1117static const unsigned int msiof1_tx_mux[] = {
1118 MSIOF1_TXD_MARK,
1119};
Marek Vasut47ef1c82024-12-23 14:34:08 +0100[diff] [blame]1120#endif
1121
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1122/* - QSPI ------------------------------------------------------------------- */
1123static const unsigned int qspi_ctrl_pins[] = {
1124 /* SPCLK, SSL */
1125 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1126};
1127static const unsigned int qspi_ctrl_mux[] = {
1128 SPCLK_MARK, SSL_MARK,
1129};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1130static const unsigned int qspi_data_pins[] = {
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1131 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1132 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23),
1133 RCAR_GP_PIN(3, 24),
1134};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1135static const unsigned int qspi_data_mux[] = {
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1136 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
1137};
1138/* - SCIF0 ------------------------------------------------------------------ */
1139static const unsigned int scif0_data_pins[] = {
1140 /* RX, TX */
1141 RCAR_GP_PIN(10, 14), RCAR_GP_PIN(10, 13),
1142};
1143static const unsigned int scif0_data_mux[] = {
1144 RX0_MARK, TX0_MARK,
1145};
1146static const unsigned int scif0_clk_pins[] = {
1147 /* SCK */
1148 RCAR_GP_PIN(10, 10),
1149};
1150static const unsigned int scif0_clk_mux[] = {
1151 SCK0_MARK,
1152};
1153static const unsigned int scif0_ctrl_pins[] = {
1154 /* RTS, CTS */
1155 RCAR_GP_PIN(10, 12), RCAR_GP_PIN(10, 11),
1156};
1157static const unsigned int scif0_ctrl_mux[] = {
1158 RTS0_N_MARK, CTS0_N_MARK,
1159};
1160/* - SCIF1 ------------------------------------------------------------------ */
1161static const unsigned int scif1_data_pins[] = {
1162 /* RX, TX */
1163 RCAR_GP_PIN(10, 19), RCAR_GP_PIN(10, 18),
1164};
1165static const unsigned int scif1_data_mux[] = {
1166 RX1_MARK, TX1_MARK,
1167};
1168static const unsigned int scif1_clk_pins[] = {
1169 /* SCK */
1170 RCAR_GP_PIN(10, 15),
1171};
1172static const unsigned int scif1_clk_mux[] = {
1173 SCK1_MARK,
1174};
1175static const unsigned int scif1_ctrl_pins[] = {
1176 /* RTS, CTS */
1177 RCAR_GP_PIN(10, 17), RCAR_GP_PIN(10, 16),
1178};
1179static const unsigned int scif1_ctrl_mux[] = {
1180 RTS1_N_MARK, CTS1_N_MARK,
1181};
1182/* - SCIF2 ------------------------------------------------------------------ */
1183static const unsigned int scif2_data_pins[] = {
1184 /* RX, TX */
1185 RCAR_GP_PIN(10, 22), RCAR_GP_PIN(10, 21),
1186};
1187static const unsigned int scif2_data_mux[] = {
1188 RX2_MARK, TX2_MARK,
1189};
1190static const unsigned int scif2_clk_pins[] = {
1191 /* SCK */
1192 RCAR_GP_PIN(10, 20),
1193};
1194static const unsigned int scif2_clk_mux[] = {
1195 SCK2_MARK,
1196};
1197/* - SCIF3 ------------------------------------------------------------------ */
1198static const unsigned int scif3_data_pins[] = {
1199 /* RX, TX */
1200 RCAR_GP_PIN(10, 25), RCAR_GP_PIN(10, 24),
1201};
1202static const unsigned int scif3_data_mux[] = {
1203 RX3_MARK, TX3_MARK,
1204};
1205static const unsigned int scif3_clk_pins[] = {
1206 /* SCK */
1207 RCAR_GP_PIN(10, 23),
1208};
1209static const unsigned int scif3_clk_mux[] = {
1210 SCK3_MARK,
1211};
1212/* - SDHI0 ------------------------------------------------------------------ */
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1213static const unsigned int sdhi0_data_pins[] = {
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1214 /* DAT[0-3] */
1215 RCAR_GP_PIN(11, 7), RCAR_GP_PIN(11, 8),
1216 RCAR_GP_PIN(11, 9), RCAR_GP_PIN(11, 10),
1217};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1218static const unsigned int sdhi0_data_mux[] = {
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1219 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
1220};
1221static const unsigned int sdhi0_ctrl_pins[] = {
1222 /* CLK, CMD */
1223 RCAR_GP_PIN(11, 5), RCAR_GP_PIN(11, 6),
1224};
1225static const unsigned int sdhi0_ctrl_mux[] = {
1226 SD0_CLK_MARK, SD0_CMD_MARK,
1227};
1228static const unsigned int sdhi0_cd_pins[] = {
1229 /* CD */
1230 RCAR_GP_PIN(11, 11),
1231};
1232static const unsigned int sdhi0_cd_mux[] = {
1233 SD0_CD_MARK,
1234};
1235static const unsigned int sdhi0_wp_pins[] = {
1236 /* WP */
1237 RCAR_GP_PIN(11, 12),
1238};
1239static const unsigned int sdhi0_wp_mux[] = {
1240 SD0_WP_MARK,
1241};
Marek Vasut47ef1c82024-12-23 14:34:08 +0100[diff] [blame]1242
1243#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1244/* - VIN0 ------------------------------------------------------------------- */
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1245static const unsigned int vin0_data_pins[] = {
1246 /* B */
1247 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1248 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1249 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1250 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1251 /* G */
1252 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
1253 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1254 RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
1255 RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
1256 /* R */
1257 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1258 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1259 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1260 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1261};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1262static const unsigned int vin0_data_mux[] = {
1263 /* B */
1264 VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK,
1265 VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
1266 VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
1267 VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
1268 /* G */
1269 VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK,
1270 VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
1271 VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
1272 VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
1273 /* R */
1274 VI0_D16_R0_MARK, VI0_D17_R1_MARK,
1275 VI0_D18_R2_MARK, VI0_D19_R3_MARK,
1276 VI0_D20_R4_MARK, VI0_D21_R5_MARK,
1277 VI0_D22_R6_MARK, VI0_D23_R7_MARK,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1278};
1279static const unsigned int vin0_data18_pins[] = {
1280 /* B */
1281 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1282 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1283 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1284 /* G */
1285 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1286 RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
1287 RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
1288 /* R */
1289 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1290 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1291 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1292};
1293static const unsigned int vin0_data18_mux[] = {
1294 /* B */
1295 VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
1296 VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
1297 VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
1298 /* G */
1299 VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
1300 VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
1301 VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
1302 /* R */
1303 VI0_D18_R2_MARK, VI0_D19_R3_MARK,
1304 VI0_D20_R4_MARK, VI0_D21_R5_MARK,
1305 VI0_D22_R6_MARK, VI0_D23_R7_MARK,
1306};
1307static const unsigned int vin0_sync_pins[] = {
1308 /* HSYNC#, VSYNC# */
1309 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1310};
1311static const unsigned int vin0_sync_mux[] = {
1312 VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
1313};
1314static const unsigned int vin0_field_pins[] = {
1315 RCAR_GP_PIN(4, 16),
1316};
1317static const unsigned int vin0_field_mux[] = {
1318 VI0_FIELD_MARK,
1319};
1320static const unsigned int vin0_clkenb_pins[] = {
1321 RCAR_GP_PIN(4, 1),
1322};
1323static const unsigned int vin0_clkenb_mux[] = {
1324 VI0_CLKENB_MARK,
1325};
1326static const unsigned int vin0_clk_pins[] = {
1327 RCAR_GP_PIN(4, 0),
1328};
1329static const unsigned int vin0_clk_mux[] = {
1330 VI0_CLK_MARK,
1331};
1332/* - VIN1 ------------------------------------------------------------------- */
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1333static const unsigned int vin1_data_pins[] = {
1334 /* B */
1335 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1336 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1337 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1338 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1339 /* G */
1340 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1341 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1342 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1343 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1344 /* R */
1345 RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1346 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1347 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1348 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1349};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1350static const unsigned int vin1_data_mux[] = {
1351 /* B */
1352 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1353 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1354 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1355 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1356 /* G */
1357 VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1358 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1359 VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
1360 VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
1361 /* R */
1362 VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1363 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1364 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1365 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1366};
1367static const unsigned int vin1_data18_pins[] = {
1368 /* B */
1369 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1370 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1371 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1372 /* G */
1373 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1374 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1375 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1376 /* R */
1377 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1378 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1379 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1380};
1381static const unsigned int vin1_data18_mux[] = {
1382 /* B */
1383 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1384 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1385 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1386 /* G */
1387 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1388 VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
1389 VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
1390 /* R */
1391 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1392 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1393 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1394};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1395static const unsigned int vin1_data_b_pins[] = {
1396 /* B */
1397 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1398 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1399 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1400 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1401 /* G */
1402 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1403 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1404 RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
1405 RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
1406 /* R */
1407 RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1408 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1409 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1410 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1411};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1412static const unsigned int vin1_data_b_mux[] = {
1413 /* B */
1414 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1415 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1416 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1417 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1418 /* G */
1419 VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1420 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1421 VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
1422 VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
1423 /* R */
1424 VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1425 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1426 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1427 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1428};
1429static const unsigned int vin1_data18_b_pins[] = {
1430 /* B */
1431 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1432 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1433 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1434 /* G */
1435 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1436 RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
1437 RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
1438 /* R */
1439 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1440 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1441 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1442};
1443static const unsigned int vin1_data18_b_mux[] = {
1444 /* B */
1445 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1446 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1447 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1448 /* G */
1449 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1450 VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
1451 VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
1452 /* R */
1453 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1454 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1455 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1456};
1457static const unsigned int vin1_sync_pins[] = {
1458 /* HSYNC#, VSYNC# */
1459 RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3),
1460};
1461static const unsigned int vin1_sync_mux[] = {
1462 VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
1463};
1464static const unsigned int vin1_field_pins[] = {
1465 RCAR_GP_PIN(5, 16),
1466};
1467static const unsigned int vin1_field_mux[] = {
1468 VI1_FIELD_MARK,
1469};
1470static const unsigned int vin1_clkenb_pins[] = {
1471 RCAR_GP_PIN(5, 1),
1472};
1473static const unsigned int vin1_clkenb_mux[] = {
1474 VI1_CLKENB_MARK,
1475};
1476static const unsigned int vin1_clk_pins[] = {
1477 RCAR_GP_PIN(5, 0),
1478};
1479static const unsigned int vin1_clk_mux[] = {
1480 VI1_CLK_MARK,
1481};
1482/* - VIN2 ------------------------------------------------------------------- */
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1483static const unsigned int vin2_data_pins[] = {
1484 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
1485 RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
1486 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1487 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
1488 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
1489 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
1490 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1491 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1492};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1493static const unsigned int vin2_data_mux[] = {
1494 VI2_D0_C0_MARK, VI2_D1_C1_MARK,
1495 VI2_D2_C2_MARK, VI2_D3_C3_MARK,
1496 VI2_D4_C4_MARK, VI2_D5_C5_MARK,
1497 VI2_D6_C6_MARK, VI2_D7_C7_MARK,
1498 VI2_D8_Y0_MARK, VI2_D9_Y1_MARK,
1499 VI2_D10_Y2_MARK, VI2_D11_Y3_MARK,
1500 VI2_D12_Y4_MARK, VI2_D13_Y5_MARK,
1501 VI2_D14_Y6_MARK, VI2_D15_Y7_MARK,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1502};
1503static const unsigned int vin2_sync_pins[] = {
1504 /* HSYNC#, VSYNC# */
1505 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
1506};
1507static const unsigned int vin2_sync_mux[] = {
1508 VI2_HSYNC_N_MARK, VI2_VSYNC_N_MARK,
1509};
1510static const unsigned int vin2_field_pins[] = {
1511 RCAR_GP_PIN(6, 16),
1512};
1513static const unsigned int vin2_field_mux[] = {
1514 VI2_FIELD_MARK,
1515};
1516static const unsigned int vin2_clkenb_pins[] = {
1517 RCAR_GP_PIN(6, 1),
1518};
1519static const unsigned int vin2_clkenb_mux[] = {
1520 VI2_CLKENB_MARK,
1521};
1522static const unsigned int vin2_clk_pins[] = {
1523 RCAR_GP_PIN(6, 0),
1524};
1525static const unsigned int vin2_clk_mux[] = {
1526 VI2_CLK_MARK,
1527};
1528/* - VIN3 ------------------------------------------------------------------- */
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1529static const unsigned int vin3_data_pins[] = {
1530 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
1531 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
1532 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1533 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
1534 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13),
1535 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
1536 RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14),
1537 RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1538};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1539static const unsigned int vin3_data_mux[] = {
1540 VI3_D0_C0_MARK, VI3_D1_C1_MARK,
1541 VI3_D2_C2_MARK, VI3_D3_C3_MARK,
1542 VI3_D4_C4_MARK, VI3_D5_C5_MARK,
1543 VI3_D6_C6_MARK, VI3_D7_C7_MARK,
1544 VI3_D8_Y0_MARK, VI3_D9_Y1_MARK,
1545 VI3_D10_Y2_MARK, VI3_D11_Y3_MARK,
1546 VI3_D12_Y4_MARK, VI3_D13_Y5_MARK,
1547 VI3_D14_Y6_MARK, VI3_D15_Y7_MARK,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1548};
1549static const unsigned int vin3_sync_pins[] = {
1550 /* HSYNC#, VSYNC# */
1551 RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3),
1552};
1553static const unsigned int vin3_sync_mux[] = {
1554 VI3_HSYNC_N_MARK, VI3_VSYNC_N_MARK,
1555};
1556static const unsigned int vin3_field_pins[] = {
1557 RCAR_GP_PIN(7, 16),
1558};
1559static const unsigned int vin3_field_mux[] = {
1560 VI3_FIELD_MARK,
1561};
1562static const unsigned int vin3_clkenb_pins[] = {
1563 RCAR_GP_PIN(7, 1),
1564};
1565static const unsigned int vin3_clkenb_mux[] = {
1566 VI3_CLKENB_MARK,
1567};
1568static const unsigned int vin3_clk_pins[] = {
1569 RCAR_GP_PIN(7, 0),
1570};
1571static const unsigned int vin3_clk_mux[] = {
1572 VI3_CLK_MARK,
1573};
1574/* - VIN4 ------------------------------------------------------------------- */
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1575static const unsigned int vin4_data_pins[] = {
1576 RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
1577 RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
1578 RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1579 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
1580 RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13),
1581 RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1582};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1583static const unsigned int vin4_data_mux[] = {
1584 VI4_D0_C0_MARK, VI4_D1_C1_MARK,
1585 VI4_D2_C2_MARK, VI4_D3_C3_MARK,
1586 VI4_D4_C4_MARK, VI4_D5_C5_MARK,
1587 VI4_D6_C6_MARK, VI4_D7_C7_MARK,
1588 VI4_D8_Y0_MARK, VI4_D9_Y1_MARK,
1589 VI4_D10_Y2_MARK, VI4_D11_Y3_MARK,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1590};
1591static const unsigned int vin4_sync_pins[] = {
1592 /* HSYNC#, VSYNC# */
1593 RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3),
1594};
1595static const unsigned int vin4_sync_mux[] = {
1596 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
1597};
1598static const unsigned int vin4_field_pins[] = {
1599 RCAR_GP_PIN(8, 16),
1600};
1601static const unsigned int vin4_field_mux[] = {
1602 VI4_FIELD_MARK,
1603};
1604static const unsigned int vin4_clkenb_pins[] = {
1605 RCAR_GP_PIN(8, 1),
1606};
1607static const unsigned int vin4_clkenb_mux[] = {
1608 VI4_CLKENB_MARK,
1609};
1610static const unsigned int vin4_clk_pins[] = {
1611 RCAR_GP_PIN(8, 0),
1612};
1613static const unsigned int vin4_clk_mux[] = {
1614 VI4_CLK_MARK,
1615};
1616/* - VIN5 ------------------------------------------------------------------- */
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1617static const unsigned int vin5_data_pins[] = {
1618 RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
1619 RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
1620 RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
1621 RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
1622 RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13),
1623 RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1624};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1625static const unsigned int vin5_data_mux[] = {
1626 VI5_D0_C0_MARK, VI5_D1_C1_MARK,
1627 VI5_D2_C2_MARK, VI5_D3_C3_MARK,
1628 VI5_D4_C4_MARK, VI5_D5_C5_MARK,
1629 VI5_D6_C6_MARK, VI5_D7_C7_MARK,
1630 VI5_D8_Y0_MARK, VI5_D9_Y1_MARK,
1631 VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1632};
1633static const unsigned int vin5_sync_pins[] = {
1634 /* HSYNC#, VSYNC# */
1635 RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3),
1636};
1637static const unsigned int vin5_sync_mux[] = {
1638 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
1639};
1640static const unsigned int vin5_field_pins[] = {
1641 RCAR_GP_PIN(9, 16),
1642};
1643static const unsigned int vin5_field_mux[] = {
1644 VI5_FIELD_MARK,
1645};
1646static const unsigned int vin5_clkenb_pins[] = {
1647 RCAR_GP_PIN(9, 1),
1648};
1649static const unsigned int vin5_clkenb_mux[] = {
1650 VI5_CLKENB_MARK,
1651};
1652static const unsigned int vin5_clk_pins[] = {
1653 RCAR_GP_PIN(9, 0),
1654};
1655static const unsigned int vin5_clk_mux[] = {
1656 VI5_CLK_MARK,
1657};
Marek Vasut47ef1c82024-12-23 14:34:08 +0100[diff] [blame]1658#endif
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1659
1660static const struct sh_pfc_pin_group pinmux_groups[] = {
1661 SH_PFC_PIN_GROUP(avb_link),
1662 SH_PFC_PIN_GROUP(avb_magic),
1663 SH_PFC_PIN_GROUP(avb_phy_int),
1664 SH_PFC_PIN_GROUP(avb_mdio),
1665 SH_PFC_PIN_GROUP(avb_mii),
1666 SH_PFC_PIN_GROUP(avb_gmii),
1667 SH_PFC_PIN_GROUP(avb_avtp_match),
Marek Vasut47ef1c82024-12-23 14:34:08 +0100[diff] [blame]1668#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1669 SH_PFC_PIN_GROUP(can0_data),
1670 SH_PFC_PIN_GROUP(can1_data),
1671 SH_PFC_PIN_GROUP(can_clk),
1672 SH_PFC_PIN_GROUP(du0_rgb666),
1673 SH_PFC_PIN_GROUP(du0_rgb888),
1674 SH_PFC_PIN_GROUP(du0_sync),
1675 SH_PFC_PIN_GROUP(du0_oddf),
1676 SH_PFC_PIN_GROUP(du0_disp),
1677 SH_PFC_PIN_GROUP(du0_cde),
1678 SH_PFC_PIN_GROUP(du1_rgb666),
1679 SH_PFC_PIN_GROUP(du1_sync),
1680 SH_PFC_PIN_GROUP(du1_oddf),
1681 SH_PFC_PIN_GROUP(du1_disp),
1682 SH_PFC_PIN_GROUP(du1_cde),
1683 SH_PFC_PIN_GROUP(intc_irq0),
1684 SH_PFC_PIN_GROUP(intc_irq1),
1685 SH_PFC_PIN_GROUP(intc_irq2),
1686 SH_PFC_PIN_GROUP(intc_irq3),
Marek Vasut47ef1c82024-12-23 14:34:08 +0100[diff] [blame]1687#endif
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1688 SH_PFC_PIN_GROUP(lbsc_cs0),
1689 SH_PFC_PIN_GROUP(lbsc_cs1),
1690 SH_PFC_PIN_GROUP(lbsc_ex_cs0),
1691 SH_PFC_PIN_GROUP(lbsc_ex_cs1),
1692 SH_PFC_PIN_GROUP(lbsc_ex_cs2),
1693 SH_PFC_PIN_GROUP(lbsc_ex_cs3),
1694 SH_PFC_PIN_GROUP(lbsc_ex_cs4),
1695 SH_PFC_PIN_GROUP(lbsc_ex_cs5),
Marek Vasut47ef1c82024-12-23 14:34:08 +0100[diff] [blame]1696#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1697 SH_PFC_PIN_GROUP(msiof0_clk),
1698 SH_PFC_PIN_GROUP(msiof0_sync),
1699 SH_PFC_PIN_GROUP(msiof0_rx),
1700 SH_PFC_PIN_GROUP(msiof0_tx),
1701 SH_PFC_PIN_GROUP(msiof1_clk),
1702 SH_PFC_PIN_GROUP(msiof1_sync),
1703 SH_PFC_PIN_GROUP(msiof1_rx),
1704 SH_PFC_PIN_GROUP(msiof1_tx),
Marek Vasut47ef1c82024-12-23 14:34:08 +0100[diff] [blame]1705#endif
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1706 SH_PFC_PIN_GROUP(qspi_ctrl),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1707 BUS_DATA_PIN_GROUP(qspi_data, 2),
1708 BUS_DATA_PIN_GROUP(qspi_data, 4),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1709 SH_PFC_PIN_GROUP(scif0_data),
1710 SH_PFC_PIN_GROUP(scif0_clk),
1711 SH_PFC_PIN_GROUP(scif0_ctrl),
1712 SH_PFC_PIN_GROUP(scif1_data),
1713 SH_PFC_PIN_GROUP(scif1_clk),
1714 SH_PFC_PIN_GROUP(scif1_ctrl),
1715 SH_PFC_PIN_GROUP(scif2_data),
1716 SH_PFC_PIN_GROUP(scif2_clk),
1717 SH_PFC_PIN_GROUP(scif3_data),
1718 SH_PFC_PIN_GROUP(scif3_clk),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1719 BUS_DATA_PIN_GROUP(sdhi0_data, 1),
1720 BUS_DATA_PIN_GROUP(sdhi0_data, 4),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1721 SH_PFC_PIN_GROUP(sdhi0_ctrl),
1722 SH_PFC_PIN_GROUP(sdhi0_cd),
1723 SH_PFC_PIN_GROUP(sdhi0_wp),
Marek Vasut47ef1c82024-12-23 14:34:08 +0100[diff] [blame]1724#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1725 BUS_DATA_PIN_GROUP(vin0_data, 24),
1726 BUS_DATA_PIN_GROUP(vin0_data, 20),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1727 SH_PFC_PIN_GROUP(vin0_data18),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1728 BUS_DATA_PIN_GROUP(vin0_data, 16),
1729 BUS_DATA_PIN_GROUP(vin0_data, 12),
1730 BUS_DATA_PIN_GROUP(vin0_data, 10),
1731 BUS_DATA_PIN_GROUP(vin0_data, 8),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1732 SH_PFC_PIN_GROUP(vin0_sync),
1733 SH_PFC_PIN_GROUP(vin0_field),
1734 SH_PFC_PIN_GROUP(vin0_clkenb),
1735 SH_PFC_PIN_GROUP(vin0_clk),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1736 BUS_DATA_PIN_GROUP(vin1_data, 24),
1737 BUS_DATA_PIN_GROUP(vin1_data, 20),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1738 SH_PFC_PIN_GROUP(vin1_data18),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1739 BUS_DATA_PIN_GROUP(vin1_data, 16),
1740 BUS_DATA_PIN_GROUP(vin1_data, 12),
1741 BUS_DATA_PIN_GROUP(vin1_data, 10),
1742 BUS_DATA_PIN_GROUP(vin1_data, 8),
1743 BUS_DATA_PIN_GROUP(vin1_data, 24, _b),
1744 BUS_DATA_PIN_GROUP(vin1_data, 20, _b),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1745 SH_PFC_PIN_GROUP(vin1_data18_b),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1746 BUS_DATA_PIN_GROUP(vin1_data, 16, _b),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1747 SH_PFC_PIN_GROUP(vin1_sync),
1748 SH_PFC_PIN_GROUP(vin1_field),
1749 SH_PFC_PIN_GROUP(vin1_clkenb),
1750 SH_PFC_PIN_GROUP(vin1_clk),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1751 BUS_DATA_PIN_GROUP(vin2_data, 16),
1752 BUS_DATA_PIN_GROUP(vin2_data, 12),
1753 BUS_DATA_PIN_GROUP(vin2_data, 10),
1754 BUS_DATA_PIN_GROUP(vin2_data, 8),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1755 SH_PFC_PIN_GROUP(vin2_sync),
1756 SH_PFC_PIN_GROUP(vin2_field),
1757 SH_PFC_PIN_GROUP(vin2_clkenb),
1758 SH_PFC_PIN_GROUP(vin2_clk),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1759 BUS_DATA_PIN_GROUP(vin3_data, 16),
1760 BUS_DATA_PIN_GROUP(vin3_data, 12),
1761 BUS_DATA_PIN_GROUP(vin3_data, 10),
1762 BUS_DATA_PIN_GROUP(vin3_data, 8),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1763 SH_PFC_PIN_GROUP(vin3_sync),
1764 SH_PFC_PIN_GROUP(vin3_field),
1765 SH_PFC_PIN_GROUP(vin3_clkenb),
1766 SH_PFC_PIN_GROUP(vin3_clk),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1767 BUS_DATA_PIN_GROUP(vin4_data, 12),
1768 BUS_DATA_PIN_GROUP(vin4_data, 10),
1769 BUS_DATA_PIN_GROUP(vin4_data, 8),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1770 SH_PFC_PIN_GROUP(vin4_sync),
1771 SH_PFC_PIN_GROUP(vin4_field),
1772 SH_PFC_PIN_GROUP(vin4_clkenb),
1773 SH_PFC_PIN_GROUP(vin4_clk),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1774 BUS_DATA_PIN_GROUP(vin5_data, 12),
1775 BUS_DATA_PIN_GROUP(vin5_data, 10),
1776 BUS_DATA_PIN_GROUP(vin5_data, 8),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1777 SH_PFC_PIN_GROUP(vin5_sync),
1778 SH_PFC_PIN_GROUP(vin5_field),
1779 SH_PFC_PIN_GROUP(vin5_clkenb),
1780 SH_PFC_PIN_GROUP(vin5_clk),
Marek Vasut47ef1c82024-12-23 14:34:08 +0100[diff] [blame]1781#endif
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1782};
1783
1784static const char * const avb_groups[] = {
1785 "avb_link",
1786 "avb_magic",
1787 "avb_phy_int",
1788 "avb_mdio",
1789 "avb_mii",
1790 "avb_gmii",
1791 "avb_avtp_match",
1792};
1793
Marek Vasut47ef1c82024-12-23 14:34:08 +0100[diff] [blame]1794#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1795static const char * const can0_groups[] = {
1796 "can0_data",
1797 "can_clk",
1798};
1799
1800static const char * const can1_groups[] = {
1801 "can1_data",
1802 "can_clk",
1803};
1804
1805static const char * const du0_groups[] = {
1806 "du0_rgb666",
1807 "du0_rgb888",
1808 "du0_sync",
1809 "du0_oddf",
1810 "du0_disp",
1811 "du0_cde",
1812};
1813
1814static const char * const du1_groups[] = {
1815 "du1_rgb666",
1816 "du1_sync",
1817 "du1_oddf",
1818 "du1_disp",
1819 "du1_cde",
1820};
1821
1822static const char * const intc_groups[] = {
1823 "intc_irq0",
1824 "intc_irq1",
1825 "intc_irq2",
1826 "intc_irq3",
1827};
Marek Vasut47ef1c82024-12-23 14:34:08 +0100[diff] [blame]1828#endif
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1829
1830static const char * const lbsc_groups[] = {
1831 "lbsc_cs0",
1832 "lbsc_cs1",
1833 "lbsc_ex_cs0",
1834 "lbsc_ex_cs1",
1835 "lbsc_ex_cs2",
1836 "lbsc_ex_cs3",
1837 "lbsc_ex_cs4",
1838 "lbsc_ex_cs5",
1839};
1840
Marek Vasut47ef1c82024-12-23 14:34:08 +0100[diff] [blame]1841#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1842static const char * const msiof0_groups[] = {
1843 "msiof0_clk",
1844 "msiof0_sync",
1845 "msiof0_rx",
1846 "msiof0_tx",
1847};
1848
1849static const char * const msiof1_groups[] = {
1850 "msiof1_clk",
1851 "msiof1_sync",
1852 "msiof1_rx",
1853 "msiof1_tx",
1854};
Marek Vasut47ef1c82024-12-23 14:34:08 +0100[diff] [blame]1855#endif
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1856
1857static const char * const qspi_groups[] = {
1858 "qspi_ctrl",
1859 "qspi_data2",
1860 "qspi_data4",
1861};
1862
1863static const char * const scif0_groups[] = {
1864 "scif0_data",
1865 "scif0_clk",
1866 "scif0_ctrl",
1867};
1868
1869static const char * const scif1_groups[] = {
1870 "scif1_data",
1871 "scif1_clk",
1872 "scif1_ctrl",
1873};
1874
1875static const char * const scif2_groups[] = {
1876 "scif2_data",
1877 "scif2_clk",
1878};
1879
1880static const char * const scif3_groups[] = {
1881 "scif3_data",
1882 "scif3_clk",
1883};
1884
1885static const char * const sdhi0_groups[] = {
1886 "sdhi0_data1",
1887 "sdhi0_data4",
1888 "sdhi0_ctrl",
1889 "sdhi0_cd",
1890 "sdhi0_wp",
1891};
1892
Marek Vasut47ef1c82024-12-23 14:34:08 +0100[diff] [blame]1893#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1894static const char * const vin0_groups[] = {
1895 "vin0_data24",
1896 "vin0_data20",
1897 "vin0_data18",
1898 "vin0_data16",
1899 "vin0_data12",
1900 "vin0_data10",
1901 "vin0_data8",
1902 "vin0_sync",
1903 "vin0_field",
1904 "vin0_clkenb",
1905 "vin0_clk",
1906};
1907
1908static const char * const vin1_groups[] = {
1909 "vin1_data24",
1910 "vin1_data20",
1911 "vin1_data18",
1912 "vin1_data16",
1913 "vin1_data12",
1914 "vin1_data10",
1915 "vin1_data8",
1916 "vin1_data24_b",
1917 "vin1_data20_b",
Marek Vasut0913c7a2019-03-04 22:26:28 +0100[diff] [blame]1918 "vin1_data18_b",
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1919 "vin1_data16_b",
1920 "vin1_sync",
1921 "vin1_field",
1922 "vin1_clkenb",
1923 "vin1_clk",
1924};
1925
1926static const char * const vin2_groups[] = {
1927 "vin2_data16",
1928 "vin2_data12",
1929 "vin2_data10",
1930 "vin2_data8",
1931 "vin2_sync",
1932 "vin2_field",
1933 "vin2_clkenb",
1934 "vin2_clk",
1935};
1936
1937static const char * const vin3_groups[] = {
1938 "vin3_data16",
1939 "vin3_data12",
1940 "vin3_data10",
1941 "vin3_data8",
1942 "vin3_sync",
1943 "vin3_field",
1944 "vin3_clkenb",
1945 "vin3_clk",
1946};
1947
1948static const char * const vin4_groups[] = {
1949 "vin4_data12",
1950 "vin4_data10",
1951 "vin4_data8",
1952 "vin4_sync",
1953 "vin4_field",
1954 "vin4_clkenb",
1955 "vin4_clk",
1956};
1957
1958static const char * const vin5_groups[] = {
1959 "vin5_data12",
1960 "vin5_data10",
1961 "vin5_data8",
1962 "vin5_sync",
1963 "vin5_field",
1964 "vin5_clkenb",
1965 "vin5_clk",
1966};
Marek Vasut47ef1c82024-12-23 14:34:08 +0100[diff] [blame]1967#endif
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1968
1969static const struct sh_pfc_function pinmux_functions[] = {
1970 SH_PFC_FUNCTION(avb),
Marek Vasut47ef1c82024-12-23 14:34:08 +0100[diff] [blame]1971#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1972 SH_PFC_FUNCTION(can0),
1973 SH_PFC_FUNCTION(can1),
1974 SH_PFC_FUNCTION(du0),
1975 SH_PFC_FUNCTION(du1),
1976 SH_PFC_FUNCTION(intc),
Marek Vasut47ef1c82024-12-23 14:34:08 +0100[diff] [blame]1977#endif
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1978 SH_PFC_FUNCTION(lbsc),
Marek Vasut47ef1c82024-12-23 14:34:08 +0100[diff] [blame]1979#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1980 SH_PFC_FUNCTION(msiof0),
1981 SH_PFC_FUNCTION(msiof1),
Marek Vasut47ef1c82024-12-23 14:34:08 +0100[diff] [blame]1982#endif
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1983 SH_PFC_FUNCTION(qspi),
1984 SH_PFC_FUNCTION(scif0),
1985 SH_PFC_FUNCTION(scif1),
1986 SH_PFC_FUNCTION(scif2),
1987 SH_PFC_FUNCTION(scif3),
1988 SH_PFC_FUNCTION(sdhi0),
Marek Vasut47ef1c82024-12-23 14:34:08 +0100[diff] [blame]1989#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1990 SH_PFC_FUNCTION(vin0),
1991 SH_PFC_FUNCTION(vin1),
1992 SH_PFC_FUNCTION(vin2),
1993 SH_PFC_FUNCTION(vin3),
1994 SH_PFC_FUNCTION(vin4),
1995 SH_PFC_FUNCTION(vin5),
Marek Vasut47ef1c82024-12-23 14:34:08 +0100[diff] [blame]1996#endif
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1997};
1998
1999static const struct pinmux_cfg_reg pinmux_config_regs[] = {
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2000 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2001 0, 0,
2002 0, 0,
2003 0, 0,
2004 GP_0_28_FN, FN_IP1_4,
2005 GP_0_27_FN, FN_IP1_3,
2006 GP_0_26_FN, FN_IP1_2,
2007 GP_0_25_FN, FN_IP1_1,
2008 GP_0_24_FN, FN_IP1_0,
2009 GP_0_23_FN, FN_IP0_23,
2010 GP_0_22_FN, FN_IP0_22,
2011 GP_0_21_FN, FN_IP0_21,
2012 GP_0_20_FN, FN_IP0_20,
2013 GP_0_19_FN, FN_IP0_19,
2014 GP_0_18_FN, FN_IP0_18,
2015 GP_0_17_FN, FN_IP0_17,
2016 GP_0_16_FN, FN_IP0_16,
2017 GP_0_15_FN, FN_IP0_15,
2018 GP_0_14_FN, FN_IP0_14,
2019 GP_0_13_FN, FN_IP0_13,
2020 GP_0_12_FN, FN_IP0_12,
2021 GP_0_11_FN, FN_IP0_11,
2022 GP_0_10_FN, FN_IP0_10,
2023 GP_0_9_FN, FN_IP0_9,
2024 GP_0_8_FN, FN_IP0_8,
2025 GP_0_7_FN, FN_IP0_7,
2026 GP_0_6_FN, FN_IP0_6,
2027 GP_0_5_FN, FN_IP0_5,
2028 GP_0_4_FN, FN_IP0_4,
2029 GP_0_3_FN, FN_IP0_3,
2030 GP_0_2_FN, FN_IP0_2,
2031 GP_0_1_FN, FN_IP0_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2032 GP_0_0_FN, FN_IP0_0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2033 },
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2034 { PINMUX_CFG_REG_VAR("GPSR1", 0xE6060008, 32,
2035 GROUP(-9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2036 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2037 GROUP(
2038 /* GP1_31_23 RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2039 GP_1_22_FN, FN_DU1_CDE,
2040 GP_1_21_FN, FN_DU1_DISP,
2041 GP_1_20_FN, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
2042 GP_1_19_FN, FN_DU1_EXVSYNC_DU1_VSYNC,
2043 GP_1_18_FN, FN_DU1_EXHSYNC_DU1_HSYNC,
2044 GP_1_17_FN, FN_DU1_DB7_C5,
2045 GP_1_16_FN, FN_DU1_DB6_C4,
2046 GP_1_15_FN, FN_DU1_DB5_C3_DATA15,
2047 GP_1_14_FN, FN_DU1_DB4_C2_DATA14,
2048 GP_1_13_FN, FN_DU1_DB3_C1_DATA13,
2049 GP_1_12_FN, FN_DU1_DB2_C0_DATA12,
2050 GP_1_11_FN, FN_IP1_16,
2051 GP_1_10_FN, FN_IP1_15,
2052 GP_1_9_FN, FN_IP1_14,
2053 GP_1_8_FN, FN_IP1_13,
2054 GP_1_7_FN, FN_IP1_12,
2055 GP_1_6_FN, FN_IP1_11,
2056 GP_1_5_FN, FN_IP1_10,
2057 GP_1_4_FN, FN_IP1_9,
2058 GP_1_3_FN, FN_IP1_8,
2059 GP_1_2_FN, FN_IP1_7,
2060 GP_1_1_FN, FN_IP1_6,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2061 GP_1_0_FN, FN_IP1_5, ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2062 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2063 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2064 GP_2_31_FN, FN_A15,
2065 GP_2_30_FN, FN_A14,
2066 GP_2_29_FN, FN_A13,
2067 GP_2_28_FN, FN_A12,
2068 GP_2_27_FN, FN_A11,
2069 GP_2_26_FN, FN_A10,
2070 GP_2_25_FN, FN_A9,
2071 GP_2_24_FN, FN_A8,
2072 GP_2_23_FN, FN_A7,
2073 GP_2_22_FN, FN_A6,
2074 GP_2_21_FN, FN_A5,
2075 GP_2_20_FN, FN_A4,
2076 GP_2_19_FN, FN_A3,
2077 GP_2_18_FN, FN_A2,
2078 GP_2_17_FN, FN_A1,
2079 GP_2_16_FN, FN_A0,
2080 GP_2_15_FN, FN_D15,
2081 GP_2_14_FN, FN_D14,
2082 GP_2_13_FN, FN_D13,
2083 GP_2_12_FN, FN_D12,
2084 GP_2_11_FN, FN_D11,
2085 GP_2_10_FN, FN_D10,
2086 GP_2_9_FN, FN_D9,
2087 GP_2_8_FN, FN_D8,
2088 GP_2_7_FN, FN_D7,
2089 GP_2_6_FN, FN_D6,
2090 GP_2_5_FN, FN_D5,
2091 GP_2_4_FN, FN_D4,
2092 GP_2_3_FN, FN_D3,
2093 GP_2_2_FN, FN_D2,
2094 GP_2_1_FN, FN_D1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2095 GP_2_0_FN, FN_D0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2096 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2097 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2098 0, 0,
2099 0, 0,
2100 0, 0,
2101 0, 0,
2102 GP_3_27_FN, FN_CS0_N,
2103 GP_3_26_FN, FN_IP1_22,
2104 GP_3_25_FN, FN_IP1_21,
2105 GP_3_24_FN, FN_IP1_20,
2106 GP_3_23_FN, FN_IP1_19,
2107 GP_3_22_FN, FN_IRQ3,
2108 GP_3_21_FN, FN_IRQ2,
2109 GP_3_20_FN, FN_IRQ1,
2110 GP_3_19_FN, FN_IRQ0,
2111 GP_3_18_FN, FN_EX_WAIT0,
2112 GP_3_17_FN, FN_WE1_N,
2113 GP_3_16_FN, FN_WE0_N,
2114 GP_3_15_FN, FN_RD_WR_N,
2115 GP_3_14_FN, FN_RD_N,
2116 GP_3_13_FN, FN_BS_N,
2117 GP_3_12_FN, FN_EX_CS5_N,
2118 GP_3_11_FN, FN_EX_CS4_N,
2119 GP_3_10_FN, FN_EX_CS3_N,
2120 GP_3_9_FN, FN_EX_CS2_N,
2121 GP_3_8_FN, FN_EX_CS1_N,
2122 GP_3_7_FN, FN_EX_CS0_N,
2123 GP_3_6_FN, FN_CS1_N_A26,
2124 GP_3_5_FN, FN_IP1_18,
2125 GP_3_4_FN, FN_IP1_17,
2126 GP_3_3_FN, FN_A19,
2127 GP_3_2_FN, FN_A18,
2128 GP_3_1_FN, FN_A17,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2129 GP_3_0_FN, FN_A16 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2130 },
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2131 { PINMUX_CFG_REG_VAR("GPSR4", 0xE6060014, 32,
2132 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2133 1, 1, 1, 1, 1, 1),
2134 GROUP(
2135 /* GP4_31_17 RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2136 GP_4_16_FN, FN_VI0_FIELD,
2137 GP_4_15_FN, FN_VI0_D11_G3_Y3,
2138 GP_4_14_FN, FN_VI0_D10_G2_Y2,
2139 GP_4_13_FN, FN_VI0_D9_G1_Y1,
2140 GP_4_12_FN, FN_VI0_D8_G0_Y0,
2141 GP_4_11_FN, FN_VI0_D7_B7_C7,
2142 GP_4_10_FN, FN_VI0_D6_B6_C6,
2143 GP_4_9_FN, FN_VI0_D5_B5_C5,
2144 GP_4_8_FN, FN_VI0_D4_B4_C4,
2145 GP_4_7_FN, FN_VI0_D3_B3_C3,
2146 GP_4_6_FN, FN_VI0_D2_B2_C2,
2147 GP_4_5_FN, FN_VI0_D1_B1_C1,
2148 GP_4_4_FN, FN_VI0_D0_B0_C0,
2149 GP_4_3_FN, FN_VI0_VSYNC_N,
2150 GP_4_2_FN, FN_VI0_HSYNC_N,
2151 GP_4_1_FN, FN_VI0_CLKENB,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2152 GP_4_0_FN, FN_VI0_CLK ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2153 },
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2154 { PINMUX_CFG_REG_VAR("GPSR5", 0xE6060018, 32,
2155 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2156 1, 1, 1, 1, 1, 1),
2157 GROUP(
2158 /* GP5_31_17 RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2159 GP_5_16_FN, FN_VI1_FIELD,
2160 GP_5_15_FN, FN_VI1_D11_G3_Y3,
2161 GP_5_14_FN, FN_VI1_D10_G2_Y2,
2162 GP_5_13_FN, FN_VI1_D9_G1_Y1,
2163 GP_5_12_FN, FN_VI1_D8_G0_Y0,
2164 GP_5_11_FN, FN_VI1_D7_B7_C7,
2165 GP_5_10_FN, FN_VI1_D6_B6_C6,
2166 GP_5_9_FN, FN_VI1_D5_B5_C5,
2167 GP_5_8_FN, FN_VI1_D4_B4_C4,
2168 GP_5_7_FN, FN_VI1_D3_B3_C3,
2169 GP_5_6_FN, FN_VI1_D2_B2_C2,
2170 GP_5_5_FN, FN_VI1_D1_B1_C1,
2171 GP_5_4_FN, FN_VI1_D0_B0_C0,
2172 GP_5_3_FN, FN_VI1_VSYNC_N,
2173 GP_5_2_FN, FN_VI1_HSYNC_N,
2174 GP_5_1_FN, FN_VI1_CLKENB,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2175 GP_5_0_FN, FN_VI1_CLK ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2176 },
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2177 { PINMUX_CFG_REG_VAR("GPSR6", 0xE606001C, 32,
2178 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2179 1, 1, 1, 1, 1, 1),
2180 GROUP(
2181 /* GP6_31_17 RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2182 GP_6_16_FN, FN_IP2_16,
2183 GP_6_15_FN, FN_IP2_15,
2184 GP_6_14_FN, FN_IP2_14,
2185 GP_6_13_FN, FN_IP2_13,
2186 GP_6_12_FN, FN_IP2_12,
2187 GP_6_11_FN, FN_IP2_11,
2188 GP_6_10_FN, FN_IP2_10,
2189 GP_6_9_FN, FN_IP2_9,
2190 GP_6_8_FN, FN_IP2_8,
2191 GP_6_7_FN, FN_IP2_7,
2192 GP_6_6_FN, FN_IP2_6,
2193 GP_6_5_FN, FN_IP2_5,
2194 GP_6_4_FN, FN_IP2_4,
2195 GP_6_3_FN, FN_IP2_3,
2196 GP_6_2_FN, FN_IP2_2,
2197 GP_6_1_FN, FN_IP2_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2198 GP_6_0_FN, FN_IP2_0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2199 },
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2200 { PINMUX_CFG_REG_VAR("GPSR7", 0xE6060020, 32,
2201 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2202 1, 1, 1, 1, 1, 1),
2203 GROUP(
2204 /* GP7_31_17 RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2205 GP_7_16_FN, FN_VI3_FIELD,
2206 GP_7_15_FN, FN_IP3_14,
2207 GP_7_14_FN, FN_VI3_D10_Y2,
2208 GP_7_13_FN, FN_IP3_13,
2209 GP_7_12_FN, FN_IP3_12,
2210 GP_7_11_FN, FN_IP3_11,
2211 GP_7_10_FN, FN_IP3_10,
2212 GP_7_9_FN, FN_IP3_9,
2213 GP_7_8_FN, FN_IP3_8,
2214 GP_7_7_FN, FN_IP3_7,
2215 GP_7_6_FN, FN_IP3_6,
2216 GP_7_5_FN, FN_IP3_5,
2217 GP_7_4_FN, FN_IP3_4,
2218 GP_7_3_FN, FN_IP3_3,
2219 GP_7_2_FN, FN_IP3_2,
2220 GP_7_1_FN, FN_IP3_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2221 GP_7_0_FN, FN_IP3_0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2222 },
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2223 { PINMUX_CFG_REG_VAR("GPSR8", 0xE6060024, 32,
2224 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2225 1, 1, 1, 1, 1, 1),
2226 GROUP(
2227 /* GP8_31_17 RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2228 GP_8_16_FN, FN_IP4_24,
2229 GP_8_15_FN, FN_IP4_23,
2230 GP_8_14_FN, FN_IP4_22,
2231 GP_8_13_FN, FN_IP4_21,
2232 GP_8_12_FN, FN_IP4_20_19,
2233 GP_8_11_FN, FN_IP4_18_17,
2234 GP_8_10_FN, FN_IP4_16_15,
2235 GP_8_9_FN, FN_IP4_14_13,
2236 GP_8_8_FN, FN_IP4_12_11,
2237 GP_8_7_FN, FN_IP4_10_9,
2238 GP_8_6_FN, FN_IP4_8_7,
2239 GP_8_5_FN, FN_IP4_6_5,
2240 GP_8_4_FN, FN_IP4_4,
2241 GP_8_3_FN, FN_IP4_3_2,
2242 GP_8_2_FN, FN_IP4_1,
2243 GP_8_1_FN, FN_IP4_0,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2244 GP_8_0_FN, FN_VI4_CLK ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2245 },
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2246 { PINMUX_CFG_REG_VAR("GPSR9", 0xE6060028, 32,
2247 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2248 1, 1, 1, 1, 1, 1),
2249 GROUP(
2250 /* GP9_31_17 RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2251 GP_9_16_FN, FN_VI5_FIELD,
2252 GP_9_15_FN, FN_VI5_D11_Y3,
2253 GP_9_14_FN, FN_VI5_D10_Y2,
2254 GP_9_13_FN, FN_VI5_D9_Y1,
2255 GP_9_12_FN, FN_IP5_11,
2256 GP_9_11_FN, FN_IP5_10,
2257 GP_9_10_FN, FN_IP5_9,
2258 GP_9_9_FN, FN_IP5_8,
2259 GP_9_8_FN, FN_IP5_7,
2260 GP_9_7_FN, FN_IP5_6,
2261 GP_9_6_FN, FN_IP5_5,
2262 GP_9_5_FN, FN_IP5_4,
2263 GP_9_4_FN, FN_IP5_3,
2264 GP_9_3_FN, FN_IP5_2,
2265 GP_9_2_FN, FN_IP5_1,
2266 GP_9_1_FN, FN_IP5_0,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2267 GP_9_0_FN, FN_VI5_CLK ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2268 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2269 { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1, GROUP(
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2270 GP_10_31_FN, FN_CAN1_RX,
2271 GP_10_30_FN, FN_CAN1_TX,
2272 GP_10_29_FN, FN_CAN_CLK,
2273 GP_10_28_FN, FN_CAN0_RX,
2274 GP_10_27_FN, FN_CAN0_TX,
2275 GP_10_26_FN, FN_SCIF_CLK,
2276 GP_10_25_FN, FN_IP6_18_17,
2277 GP_10_24_FN, FN_IP6_16,
2278 GP_10_23_FN, FN_IP6_15_14,
2279 GP_10_22_FN, FN_IP6_13_12,
2280 GP_10_21_FN, FN_IP6_11_10,
2281 GP_10_20_FN, FN_IP6_9_8,
2282 GP_10_19_FN, FN_RX1,
2283 GP_10_18_FN, FN_TX1,
2284 GP_10_17_FN, FN_RTS1_N,
2285 GP_10_16_FN, FN_CTS1_N,
2286 GP_10_15_FN, FN_SCK1,
2287 GP_10_14_FN, FN_RX0,
2288 GP_10_13_FN, FN_TX0,
2289 GP_10_12_FN, FN_RTS0_N,
2290 GP_10_11_FN, FN_CTS0_N,
2291 GP_10_10_FN, FN_SCK0,
2292 GP_10_9_FN, FN_IP6_7,
2293 GP_10_8_FN, FN_IP6_6,
2294 GP_10_7_FN, FN_HCTS1_N,
2295 GP_10_6_FN, FN_IP6_5,
2296 GP_10_5_FN, FN_IP6_4,
2297 GP_10_4_FN, FN_IP6_3,
2298 GP_10_3_FN, FN_IP6_2,
2299 GP_10_2_FN, FN_HRTS0_N,
2300 GP_10_1_FN, FN_IP6_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2301 GP_10_0_FN, FN_IP6_0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2302 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2303 { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1, GROUP(
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2304 0, 0,
2305 0, 0,
2306 GP_11_29_FN, FN_AVS2,
2307 GP_11_28_FN, FN_AVS1,
2308 GP_11_27_FN, FN_ADICHS2,
2309 GP_11_26_FN, FN_ADICHS1,
2310 GP_11_25_FN, FN_ADICHS0,
2311 GP_11_24_FN, FN_ADIDATA,
2312 GP_11_23_FN, FN_ADICS_SAMP,
2313 GP_11_22_FN, FN_ADICLK,
2314 GP_11_21_FN, FN_IP7_20,
2315 GP_11_20_FN, FN_IP7_19,
2316 GP_11_19_FN, FN_IP7_18,
2317 GP_11_18_FN, FN_IP7_17,
2318 GP_11_17_FN, FN_IP7_16,
2319 GP_11_16_FN, FN_IP7_15_14,
2320 GP_11_15_FN, FN_IP7_13_12,
2321 GP_11_14_FN, FN_IP7_11_10,
2322 GP_11_13_FN, FN_IP7_9_8,
2323 GP_11_12_FN, FN_SD0_WP,
2324 GP_11_11_FN, FN_SD0_CD,
2325 GP_11_10_FN, FN_SD0_DAT3,
2326 GP_11_9_FN, FN_SD0_DAT2,
2327 GP_11_8_FN, FN_SD0_DAT1,
2328 GP_11_7_FN, FN_SD0_DAT0,
2329 GP_11_6_FN, FN_SD0_CMD,
2330 GP_11_5_FN, FN_SD0_CLK,
2331 GP_11_4_FN, FN_IP7_7,
2332 GP_11_3_FN, FN_IP7_6,
2333 GP_11_2_FN, FN_IP7_5_4,
2334 GP_11_1_FN, FN_IP7_3_2,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2335 GP_11_0_FN, FN_IP7_1_0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2336 },
2337 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2338 GROUP(-8,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2339 1, 1, 1, 1, 1, 1, 1, 1,
2340 1, 1, 1, 1, 1, 1, 1, 1,
2341 1, 1, 1, 1, 1, 1, 1, 1),
2342 GROUP(
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2343 /* IP0_31_24 [8] RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2344 /* IP0_23 [1] */
2345 FN_DU0_DB7_C5, 0,
2346 /* IP0_22 [1] */
2347 FN_DU0_DB6_C4, 0,
2348 /* IP0_21 [1] */
2349 FN_DU0_DB5_C3, 0,
2350 /* IP0_20 [1] */
2351 FN_DU0_DB4_C2, 0,
2352 /* IP0_19 [1] */
2353 FN_DU0_DB3_C1, 0,
2354 /* IP0_18 [1] */
2355 FN_DU0_DB2_C0, 0,
2356 /* IP0_17 [1] */
2357 FN_DU0_DB1, 0,
2358 /* IP0_16 [1] */
2359 FN_DU0_DB0, 0,
2360 /* IP0_15 [1] */
2361 FN_DU0_DG7_Y3_DATA15, 0,
2362 /* IP0_14 [1] */
2363 FN_DU0_DG6_Y2_DATA14, 0,
2364 /* IP0_13 [1] */
2365 FN_DU0_DG5_Y1_DATA13, 0,
2366 /* IP0_12 [1] */
2367 FN_DU0_DG4_Y0_DATA12, 0,
2368 /* IP0_11 [1] */
2369 FN_DU0_DG3_C7_DATA11, 0,
2370 /* IP0_10 [1] */
2371 FN_DU0_DG2_C6_DATA10, 0,
2372 /* IP0_9 [1] */
2373 FN_DU0_DG1_DATA9, 0,
2374 /* IP0_8 [1] */
2375 FN_DU0_DG0_DATA8, 0,
2376 /* IP0_7 [1] */
2377 FN_DU0_DR7_Y9_DATA7, 0,
2378 /* IP0_6 [1] */
2379 FN_DU0_DR6_Y8_DATA6, 0,
2380 /* IP0_5 [1] */
2381 FN_DU0_DR5_Y7_DATA5, 0,
2382 /* IP0_4 [1] */
2383 FN_DU0_DR4_Y6_DATA4, 0,
2384 /* IP0_3 [1] */
2385 FN_DU0_DR3_Y5_DATA3, 0,
2386 /* IP0_2 [1] */
2387 FN_DU0_DR2_Y4_DATA2, 0,
2388 /* IP0_1 [1] */
2389 FN_DU0_DR1_DATA1, 0,
2390 /* IP0_0 [1] */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2391 FN_DU0_DR0_DATA0, 0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2392 },
2393 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2394 GROUP(-9, 1, 1, 1, 1, 1, 1, 1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2395 1, 1, 1, 1, 1, 1, 1, 1,
2396 1, 1, 1, 1, 1, 1, 1, 1),
2397 GROUP(
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2398 /* IP1_31_23 [9] RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2399 /* IP1_22 [1] */
2400 FN_A25, FN_SSL,
2401 /* IP1_21 [1] */
2402 FN_A24, FN_SPCLK,
2403 /* IP1_20 [1] */
2404 FN_A23, FN_IO3,
2405 /* IP1_19 [1] */
2406 FN_A22, FN_IO2,
2407 /* IP1_18 [1] */
2408 FN_A21, FN_MISO_IO1,
2409 /* IP1_17 [1] */
2410 FN_A20, FN_MOSI_IO0,
2411 /* IP1_16 [1] */
2412 FN_DU1_DG7_Y3_DATA11, 0,
2413 /* IP1_15 [1] */
2414 FN_DU1_DG6_Y2_DATA10, 0,
2415 /* IP1_14 [1] */
2416 FN_DU1_DG5_Y1_DATA9, 0,
2417 /* IP1_13 [1] */
2418 FN_DU1_DG4_Y0_DATA8, 0,
2419 /* IP1_12 [1] */
2420 FN_DU1_DG3_C7_DATA7, 0,
2421 /* IP1_11 [1] */
2422 FN_DU1_DG2_C6_DATA6, 0,
2423 /* IP1_10 [1] */
2424 FN_DU1_DR7_DATA5, 0,
2425 /* IP1_9 [1] */
2426 FN_DU1_DR6_DATA4, 0,
2427 /* IP1_8 [1] */
2428 FN_DU1_DR5_Y7_DATA3, 0,
2429 /* IP1_7 [1] */
2430 FN_DU1_DR4_Y6_DATA2, 0,
2431 /* IP1_6 [1] */
2432 FN_DU1_DR3_Y5_DATA1, 0,
2433 /* IP1_5 [1] */
2434 FN_DU1_DR2_Y4_DATA0, 0,
2435 /* IP1_4 [1] */
2436 FN_DU0_CDE, 0,
2437 /* IP1_3 [1] */
2438 FN_DU0_DISP, 0,
2439 /* IP1_2 [1] */
2440 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0,
2441 /* IP1_1 [1] */
2442 FN_DU0_EXVSYNC_DU0_VSYNC, 0,
2443 /* IP1_0 [1] */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2444 FN_DU0_EXHSYNC_DU0_HSYNC, 0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2445 },
2446 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2447 GROUP(-15, 1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2448 1, 1, 1, 1, 1, 1, 1, 1,
2449 1, 1, 1, 1, 1, 1, 1, 1),
2450 GROUP(
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2451 /* IP2_31_17 [15] RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2452 /* IP2_16 [1] */
2453 FN_VI2_FIELD, FN_AVB_TXD2,
2454 /* IP2_15 [1] */
2455 FN_VI2_D11_Y3, FN_AVB_TXD1,
2456 /* IP2_14 [1] */
2457 FN_VI2_D10_Y2, FN_AVB_TXD0,
2458 /* IP2_13 [1] */
2459 FN_VI2_D9_Y1, FN_AVB_TX_EN,
2460 /* IP2_12 [1] */
2461 FN_VI2_D8_Y0, FN_AVB_TXD3,
2462 /* IP2_11 [1] */
2463 FN_VI2_D7_C7, FN_AVB_COL,
2464 /* IP2_10 [1] */
2465 FN_VI2_D6_C6, FN_AVB_RX_ER,
2466 /* IP2_9 [1] */
2467 FN_VI2_D5_C5, FN_AVB_RXD7,
2468 /* IP2_8 [1] */
2469 FN_VI2_D4_C4, FN_AVB_RXD6,
2470 /* IP2_7 [1] */
2471 FN_VI2_D3_C3, FN_AVB_RXD5,
2472 /* IP2_6 [1] */
2473 FN_VI2_D2_C2, FN_AVB_RXD4,
2474 /* IP2_5 [1] */
2475 FN_VI2_D1_C1, FN_AVB_RXD3,
2476 /* IP2_4 [1] */
2477 FN_VI2_D0_C0, FN_AVB_RXD2,
2478 /* IP2_3 [1] */
2479 FN_VI2_VSYNC_N, FN_AVB_RXD1,
2480 /* IP2_2 [1] */
2481 FN_VI2_HSYNC_N, FN_AVB_RXD0,
2482 /* IP2_1 [1] */
2483 FN_VI2_CLKENB, FN_AVB_RX_DV,
2484 /* IP2_0 [1] */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2485 FN_VI2_CLK, FN_AVB_RX_CLK ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2486 },
2487 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2488 GROUP(-17, 1, 1, 1, 1, 1, 1, 1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2489 1, 1, 1, 1, 1, 1, 1, 1),
2490 GROUP(
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2491 /* IP3_31_15 [17] RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2492 /* IP3_14 [1] */
2493 FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
2494 /* IP3_13 [1] */
2495 FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
2496 /* IP3_12 [1] */
2497 FN_VI3_D8_Y0, FN_AVB_CRS,
2498 /* IP3_11 [1] */
2499 FN_VI3_D7_C7, FN_AVB_PHY_INT,
2500 /* IP3_10 [1] */
2501 FN_VI3_D6_C6, FN_AVB_MAGIC,
2502 /* IP3_9 [1] */
2503 FN_VI3_D5_C5, FN_AVB_LINK,
2504 /* IP3_8 [1] */
2505 FN_VI3_D4_C4, FN_AVB_MDIO,
2506 /* IP3_7 [1] */
2507 FN_VI3_D3_C3, FN_AVB_MDC,
2508 /* IP3_6 [1] */
2509 FN_VI3_D2_C2, FN_AVB_GTX_CLK,
2510 /* IP3_5 [1] */
2511 FN_VI3_D1_C1, FN_AVB_TX_ER,
2512 /* IP3_4 [1] */
2513 FN_VI3_D0_C0, FN_AVB_TXD7,
2514 /* IP3_3 [1] */
2515 FN_VI3_VSYNC_N, FN_AVB_TXD6,
2516 /* IP3_2 [1] */
2517 FN_VI3_HSYNC_N, FN_AVB_TXD5,
2518 /* IP3_1 [1] */
2519 FN_VI3_CLKENB, FN_AVB_TXD4,
2520 /* IP3_0 [1] */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2521 FN_VI3_CLK, FN_AVB_TX_CLK ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2522 },
2523 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2524 GROUP(-7, 1, 1, 1, 1, 2, 2, 2,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2525 2, 2, 2, 2, 2, 1, 2, 1, 1),
2526 GROUP(
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2527 /* IP4_31_25 [7] RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2528 /* IP4_24 [1] */
2529 FN_VI4_FIELD, FN_VI3_D15_Y7,
2530 /* IP4_23 [1] */
2531 FN_VI4_D11_Y3, FN_VI3_D14_Y6,
2532 /* IP4_22 [1] */
2533 FN_VI4_D10_Y2, FN_VI3_D13_Y5,
2534 /* IP4_21 [1] */
2535 FN_VI4_D9_Y1, FN_VI3_D12_Y4,
2536 /* IP4_20_19 [2] */
2537 FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7, 0,
2538 /* IP4_18_17 [2] */
2539 FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6, 0,
2540 /* IP4_16_15 [2] */
2541 FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5, 0,
2542 /* IP4_14_13 [2] */
2543 FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4, 0,
2544 /* IP4_12_11 [2] */
2545 FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7, 0,
2546 /* IP4_10_9 [2] */
2547 FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6, 0,
2548 /* IP4_8_7 [2] */
2549 FN_VI4_D2_C2, 0, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
2550 /* IP4_6_5 [2] */
2551 FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4, 0,
2552 /* IP4_4 [1] */
2553 FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
2554 /* IP4_3_2 [2] */
2555 FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, 0, 0,
2556 /* IP4_1 [1] */
2557 FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
2558 /* IP4_0 [1] */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2559 FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2560 },
2561 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2562 GROUP(-20, 1, 1, 1, 1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2563 1, 1, 1, 1, 1, 1, 1, 1),
2564 GROUP(
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2565 /* IP5_31_12 [20] RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2566 /* IP5_11 [1] */
2567 FN_VI5_D8_Y0, FN_VI1_D23_R7,
2568 /* IP5_10 [1] */
2569 FN_VI5_D7_C7, FN_VI1_D22_R6,
2570 /* IP5_9 [1] */
2571 FN_VI5_D6_C6, FN_VI1_D21_R5,
2572 /* IP5_8 [1] */
2573 FN_VI5_D5_C5, FN_VI1_D20_R4,
2574 /* IP5_7 [1] */
2575 FN_VI5_D4_C4, FN_VI1_D19_R3,
2576 /* IP5_6 [1] */
2577 FN_VI5_D3_C3, FN_VI1_D18_R2,
2578 /* IP5_5 [1] */
2579 FN_VI5_D2_C2, FN_VI1_D17_R1,
2580 /* IP5_4 [1] */
2581 FN_VI5_D1_C1, FN_VI1_D16_R0,
2582 /* IP5_3 [1] */
2583 FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
2584 /* IP5_2 [1] */
2585 FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B,
2586 /* IP5_1 [1] */
2587 FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
2588 /* IP5_0 [1] */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2589 FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2590 },
2591 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2592 GROUP(-13, 2, 1, 2, 2, 2, 2,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2593 1, 1, 1, 1, 1, 1, 1, 1),
2594 GROUP(
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2595 /* IP6_31_19 [13] RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2596 /* IP6_18_17 [2] */
2597 FN_DREQ1_N, FN_RX3, 0, 0,
2598 /* IP6_16 [1] */
2599 FN_TX3, 0,
2600 /* IP6_15_14 [2] */
2601 FN_DACK1, FN_SCK3, 0, 0,
2602 /* IP6_13_12 [2] */
2603 FN_DREQ0_N, FN_RX2, 0, 0,
2604 /* IP6_11_10 [2] */
2605 FN_DACK0, FN_TX2, 0, 0,
2606 /* IP6_9_8 [2] */
2607 FN_DRACK0, FN_SCK2, 0, 0,
2608 /* IP6_7 [1] */
2609 FN_MSIOF1_RXD, FN_HRX1,
2610 /* IP6_6 [1] */
2611 FN_MSIOF1_TXD, FN_HTX1,
2612 /* IP6_5 [1] */
2613 FN_MSIOF1_SYNC, FN_HRTS1_N,
2614 /* IP6_4 [1] */
2615 FN_MSIOF1_SCK, FN_HSCK1,
2616 /* IP6_3 [1] */
2617 FN_MSIOF0_RXD, FN_HRX0,
2618 /* IP6_2 [1] */
2619 FN_MSIOF0_TXD, FN_HTX0,
2620 /* IP6_1 [1] */
2621 FN_MSIOF0_SYNC, FN_HCTS0_N,
2622 /* IP6_0 [1] */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2623 FN_MSIOF0_SCK, FN_HSCK0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2624 },
2625 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2626 GROUP(-11, 1, 1, 1, 1, 1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2627 2, 2, 2, 2,
2628 1, 1, 2, 2, 2),
2629 GROUP(
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2630 /* IP7_31_21 [11] RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2631 /* IP7_20 [1] */
2632 FN_AUDIO_CLKB, 0,
2633 /* IP7_19 [1] */
2634 FN_AUDIO_CLKA, 0,
2635 /* IP7_18 [1] */
2636 FN_AUDIO_CLKOUT, 0,
2637 /* IP7_17 [1] */
2638 FN_SSI_SDATA4, 0,
2639 /* IP7_16 [1] */
2640 FN_SSI_WS4, 0,
2641 /* IP7_15_14 [2] */
2642 FN_SSI_SCK4, FN_TPU0TO3, 0, 0,
2643 /* IP7_13_12 [2] */
2644 FN_SSI_SDATA3, FN_TPU0TO2, 0, 0,
2645 /* IP7_11_10 [2] */
2646 FN_SSI_WS34, FN_TPU0TO1, 0, 0,
2647 /* IP7_9_8 [2] */
2648 FN_SSI_SCK34, FN_TPU0TO0, 0, 0,
2649 /* IP7_7 [1] */
2650 FN_PWM4, 0,
2651 /* IP7_6 [1] */
2652 FN_PWM3, 0,
2653 /* IP7_5_4 [2] */
2654 FN_PWM2, FN_TCLK3, FN_FSO_TOE, 0,
2655 /* IP7_3_2 [2] */
2656 FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0,
2657 /* IP7_1_0 [2] */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2658 FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2659 },
Marek Vasut78861462023-09-17 16:08:38 +0200[diff] [blame]2660 { /* sentinel */ }
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2661};
2662
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2663static const struct pinmux_bias_reg pinmux_bias_regs[] = {
2664 { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
2665 [ 0] = RCAR_GP_PIN(0, 0), /* DU0_DR0_DATA0 */
2666 [ 1] = RCAR_GP_PIN(0, 1), /* DU0_DR1_DATA1 */
2667 [ 2] = RCAR_GP_PIN(0, 2), /* DU0_DR2_Y4_DATA2 */
2668 [ 3] = RCAR_GP_PIN(0, 3), /* DU0_DR3_Y5_DATA3 */
2669 [ 4] = RCAR_GP_PIN(0, 4), /* DU0_DR4_Y6_DATA4 */
2670 [ 5] = RCAR_GP_PIN(0, 5), /* DU0_DR5_Y7_DATA5 */
2671 [ 6] = RCAR_GP_PIN(0, 6), /* DU0_DR6_Y8_DATA6 */
2672 [ 7] = RCAR_GP_PIN(0, 7), /* DU0_DR7_Y9_DATA7 */
2673 [ 8] = RCAR_GP_PIN(0, 8), /* DU0_DG0_DATA8 */
2674 [ 9] = RCAR_GP_PIN(0, 9), /* DU0_DG1_DATA9 */
2675 [10] = RCAR_GP_PIN(0, 10), /* DU0_DG2_C6_DATA10 */
2676 [11] = RCAR_GP_PIN(0, 11), /* DU0_DG3_C7_DATA11 */
2677 [12] = RCAR_GP_PIN(0, 12), /* DU0_DG4_Y0_DATA12 */
2678 [13] = RCAR_GP_PIN(0, 13), /* DU0_DG5_Y1_DATA13 */
2679 [14] = RCAR_GP_PIN(0, 14), /* DU0_DG6_Y2_DATA14 */
2680 [15] = RCAR_GP_PIN(0, 15), /* DU0_DG7_Y3_DATA15 */
2681 [16] = RCAR_GP_PIN(0, 16), /* DU0_DB0 */
2682 [17] = RCAR_GP_PIN(0, 17), /* DU0_DB1 */
2683 [18] = RCAR_GP_PIN(0, 18), /* DU0_DB2_C0 */
2684 [19] = RCAR_GP_PIN(0, 19), /* DU0_DB3_C1 */
2685 [20] = RCAR_GP_PIN(0, 20), /* DU0_DB4_C2 */
2686 [21] = RCAR_GP_PIN(0, 21), /* DU0_DB5_C3 */
2687 [22] = RCAR_GP_PIN(0, 22), /* DU0_DB6_C4 */
2688 [23] = RCAR_GP_PIN(0, 23), /* DU0_DB7_C5 */
2689 [24] = RCAR_GP_PIN(0, 24), /* DU0_EXHSYNC/DU0_HSYNC */
2690 [25] = RCAR_GP_PIN(0, 25), /* DU0_EXVSYNC/DU0_VSYNC */
2691 [26] = RCAR_GP_PIN(0, 26), /* DU0_EXODDF/DU0_ODDF_DISP_CDE */
2692 [27] = RCAR_GP_PIN(0, 27), /* DU0_DISP */
2693 [28] = RCAR_GP_PIN(0, 28), /* DU0_CDE */
2694 [29] = SH_PFC_PIN_NONE,
2695 [30] = SH_PFC_PIN_NONE,
2696 [31] = SH_PFC_PIN_NONE,
2697 } },
2698 { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
2699 [ 0] = RCAR_GP_PIN(1, 0), /* DU1_DR2_Y4_DATA0 */
2700 [ 1] = RCAR_GP_PIN(1, 1), /* DU1_DR3_Y5_DATA1 */
2701 [ 2] = RCAR_GP_PIN(1, 2), /* DU1_DR4_Y6_DATA2 */
2702 [ 3] = RCAR_GP_PIN(1, 3), /* DU1_DR5_Y7_DATA3 */
2703 [ 4] = RCAR_GP_PIN(1, 4), /* DU1_DR6_DATA4 */
2704 [ 5] = RCAR_GP_PIN(1, 5), /* DU1_DR7_DATA5 */
2705 [ 6] = RCAR_GP_PIN(1, 6), /* DU1_DG2_C6_DATA6 */
2706 [ 7] = RCAR_GP_PIN(1, 7), /* DU1_DG3_C7_DATA7 */
2707 [ 8] = RCAR_GP_PIN(1, 8), /* DU1_DG4_Y0_DATA8 */
2708 [ 9] = RCAR_GP_PIN(1, 9), /* DU1_DG5_Y1_DATA9 */
2709 [10] = RCAR_GP_PIN(1, 10), /* DU1_DG6_Y2_DATA10 */
2710 [11] = RCAR_GP_PIN(1, 11), /* DU1_DG7_Y3_DATA11 */
2711 [12] = RCAR_GP_PIN(1, 12), /* DU1_DB2_C0_DATA12 */
2712 [13] = RCAR_GP_PIN(1, 13), /* DU1_DB3_C1_DATA13 */
2713 [14] = RCAR_GP_PIN(1, 14), /* DU1_DB4_C2_DATA14 */
2714 [15] = RCAR_GP_PIN(1, 15), /* DU1_DB5_C3_DATA15 */
2715 [16] = RCAR_GP_PIN(1, 16), /* DU1_DB6_C4 */
2716 [17] = RCAR_GP_PIN(1, 17), /* DU1_DB7_C5 */
2717 [18] = RCAR_GP_PIN(1, 18), /* DU1_EXHSYNC/DU1_HSYNC */
2718 [19] = RCAR_GP_PIN(1, 19), /* DU1_EXVSYNC/DU1_VSYNC */
2719 [20] = RCAR_GP_PIN(1, 20), /* DU1_EXODDF/DU1_ODDF_DISP_CDE */
2720 [21] = RCAR_GP_PIN(1, 21), /* DU1_DISP */
2721 [22] = RCAR_GP_PIN(1, 22), /* DU1_CDE */
2722 [23] = SH_PFC_PIN_NONE,
2723 [24] = SH_PFC_PIN_NONE,
2724 [25] = SH_PFC_PIN_NONE,
2725 [26] = SH_PFC_PIN_NONE,
2726 [27] = SH_PFC_PIN_NONE,
2727 [28] = SH_PFC_PIN_NONE,
2728 [29] = SH_PFC_PIN_NONE,
2729 [30] = SH_PFC_PIN_NONE,
2730 [31] = SH_PFC_PIN_NONE,
2731 } },
2732 { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
2733 [ 0] = RCAR_GP_PIN(2, 0), /* D0 */
2734 [ 1] = RCAR_GP_PIN(2, 1), /* D1 */
2735 [ 2] = RCAR_GP_PIN(2, 2), /* D2 */
2736 [ 3] = RCAR_GP_PIN(2, 3), /* D3 */
2737 [ 4] = RCAR_GP_PIN(2, 4), /* D4 */
2738 [ 5] = RCAR_GP_PIN(2, 5), /* D5 */
2739 [ 6] = RCAR_GP_PIN(2, 6), /* D6 */
2740 [ 7] = RCAR_GP_PIN(2, 7), /* D7 */
2741 [ 8] = RCAR_GP_PIN(2, 8), /* D8 */
2742 [ 9] = RCAR_GP_PIN(2, 9), /* D9 */
2743 [10] = RCAR_GP_PIN(2, 10), /* D10 */
2744 [11] = RCAR_GP_PIN(2, 11), /* D11 */
2745 [12] = RCAR_GP_PIN(2, 12), /* D12 */
2746 [13] = RCAR_GP_PIN(2, 13), /* D13 */
2747 [14] = RCAR_GP_PIN(2, 14), /* D14 */
2748 [15] = RCAR_GP_PIN(2, 15), /* D15 */
2749 [16] = RCAR_GP_PIN(2, 16), /* A0 */
2750 [17] = RCAR_GP_PIN(2, 17), /* A1 */
2751 [18] = RCAR_GP_PIN(2, 18), /* A2 */
2752 [19] = RCAR_GP_PIN(2, 19), /* A3 */
2753 [20] = RCAR_GP_PIN(2, 20), /* A4 */
2754 [21] = RCAR_GP_PIN(2, 21), /* A5 */
2755 [22] = RCAR_GP_PIN(2, 22), /* A6 */
2756 [23] = RCAR_GP_PIN(2, 23), /* A7 */
2757 [24] = RCAR_GP_PIN(2, 24), /* A8 */
2758 [25] = RCAR_GP_PIN(2, 25), /* A9 */
2759 [26] = RCAR_GP_PIN(2, 26), /* A10 */
2760 [27] = RCAR_GP_PIN(2, 27), /* A11 */
2761 [28] = RCAR_GP_PIN(2, 28), /* A12 */
2762 [29] = RCAR_GP_PIN(2, 29), /* A13 */
2763 [30] = RCAR_GP_PIN(2, 30), /* A14 */
2764 [31] = RCAR_GP_PIN(2, 31), /* A15 */
2765 } },
2766 { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
2767 [ 0] = RCAR_GP_PIN(3, 0), /* A16 */
2768 [ 1] = RCAR_GP_PIN(3, 1), /* A17 */
2769 [ 2] = RCAR_GP_PIN(3, 2), /* A18 */
2770 [ 3] = RCAR_GP_PIN(3, 3), /* A19 */
2771 [ 4] = RCAR_GP_PIN(3, 4), /* A20 */
2772 [ 5] = RCAR_GP_PIN(3, 5), /* A21 */
2773 [ 6] = RCAR_GP_PIN(3, 6), /* CS1#/A26 */
2774 [ 7] = RCAR_GP_PIN(3, 7), /* EX_CS0# */
2775 [ 8] = RCAR_GP_PIN(3, 8), /* EX_CS1# */
2776 [ 9] = RCAR_GP_PIN(3, 9), /* EX_CS2# */
2777 [10] = RCAR_GP_PIN(3, 10), /* EX_CS3# */
2778 [11] = RCAR_GP_PIN(3, 11), /* EX_CS4# */
2779 [12] = RCAR_GP_PIN(3, 12), /* EX_CS5# */
2780 [13] = RCAR_GP_PIN(3, 13), /* BS# */
2781 [14] = RCAR_GP_PIN(3, 14), /* RD# */
2782 [15] = RCAR_GP_PIN(3, 15), /* RD/WR# */
2783 [16] = RCAR_GP_PIN(3, 16), /* WE0# */
2784 [17] = RCAR_GP_PIN(3, 17), /* WE1# */
2785 [18] = RCAR_GP_PIN(3, 18), /* EX_WAIT0 */
2786 [19] = RCAR_GP_PIN(3, 19), /* IRQ0 */
2787 [20] = RCAR_GP_PIN(3, 20), /* IRQ1 */
2788 [21] = RCAR_GP_PIN(3, 21), /* IRQ2 */
2789 [22] = RCAR_GP_PIN(3, 22), /* IRQ3 */
2790 [23] = RCAR_GP_PIN(3, 23), /* A22 */
2791 [24] = RCAR_GP_PIN(3, 24), /* A23 */
2792 [25] = RCAR_GP_PIN(3, 25), /* A24 */
2793 [26] = RCAR_GP_PIN(3, 26), /* A25 */
2794 [27] = RCAR_GP_PIN(3, 27), /* CS0# */
2795 [28] = SH_PFC_PIN_NONE,
2796 [29] = SH_PFC_PIN_NONE,
2797 [30] = SH_PFC_PIN_NONE,
2798 [31] = SH_PFC_PIN_NONE,
2799 } },
2800 { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
2801 [ 0] = RCAR_GP_PIN(4, 0), /* VI0_CLK */
2802 [ 1] = RCAR_GP_PIN(4, 1), /* VI0_CLKENB */
2803 [ 2] = RCAR_GP_PIN(4, 2), /* VI0_HSYNC# */
2804 [ 3] = RCAR_GP_PIN(4, 3), /* VI0_VSYNC# */
2805 [ 4] = RCAR_GP_PIN(4, 4), /* VI0_D0_B0_C0 */
2806 [ 5] = RCAR_GP_PIN(4, 5), /* VI0_D1_B1_C1 */
2807 [ 6] = RCAR_GP_PIN(4, 6), /* VI0_D2_B2_C2 */
2808 [ 7] = RCAR_GP_PIN(4, 7), /* VI0_D3_B3_C3 */
2809 [ 8] = RCAR_GP_PIN(4, 8), /* VI0_D4_B4_C4 */
2810 [ 9] = RCAR_GP_PIN(4, 9), /* VI0_D5_B5_C5 */
2811 [10] = RCAR_GP_PIN(4, 10), /* VI0_D6_B6_C6 */
2812 [11] = RCAR_GP_PIN(4, 11), /* VI0_D7_B7_C7 */
2813 [12] = RCAR_GP_PIN(4, 12), /* VI0_D8_G0_Y0 */
2814 [13] = RCAR_GP_PIN(4, 13), /* VI0_D9_G1_Y1 */
2815 [14] = RCAR_GP_PIN(4, 14), /* VI0_D10_G2_Y2 */
2816 [15] = RCAR_GP_PIN(4, 15), /* VI0_D11_G3_Y3 */
2817 [16] = RCAR_GP_PIN(4, 16), /* VI0_FIELD */
2818 [17] = SH_PFC_PIN_NONE,
2819 [18] = SH_PFC_PIN_NONE,
2820 [19] = SH_PFC_PIN_NONE,
2821 [20] = SH_PFC_PIN_NONE,
2822 [21] = SH_PFC_PIN_NONE,
2823 [22] = SH_PFC_PIN_NONE,
2824 [23] = SH_PFC_PIN_NONE,
2825 [24] = SH_PFC_PIN_NONE,
2826 [25] = SH_PFC_PIN_NONE,
2827 [26] = SH_PFC_PIN_NONE,
2828 [27] = SH_PFC_PIN_NONE,
2829 [28] = SH_PFC_PIN_NONE,
2830 [29] = SH_PFC_PIN_NONE,
2831 [30] = SH_PFC_PIN_NONE,
2832 [31] = SH_PFC_PIN_NONE,
2833 } },
2834 { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
2835 [ 0] = RCAR_GP_PIN(5, 0), /* VI1_CLK */
2836 [ 1] = RCAR_GP_PIN(5, 1), /* VI1_CLKENB */
2837 [ 2] = RCAR_GP_PIN(5, 2), /* VI1_HSYNC# */
2838 [ 3] = RCAR_GP_PIN(5, 3), /* VI1_VSYNC# */
2839 [ 4] = RCAR_GP_PIN(5, 4), /* VI1_D0_B0_C0 */
2840 [ 5] = RCAR_GP_PIN(5, 5), /* VI1_D1_B1_C1 */
2841 [ 6] = RCAR_GP_PIN(5, 6), /* VI1_D2_B2_C2 */
2842 [ 7] = RCAR_GP_PIN(5, 7), /* VI1_D3_B3_C3 */
2843 [ 8] = RCAR_GP_PIN(5, 8), /* VI1_D4_B4_C4 */
2844 [ 9] = RCAR_GP_PIN(5, 9), /* VI1_D5_B5_C5 */
2845 [10] = RCAR_GP_PIN(5, 10), /* VI1_D6_B6_C6 */
2846 [11] = RCAR_GP_PIN(5, 11), /* VI1_D7_B7_C7 */
2847 [12] = RCAR_GP_PIN(5, 12), /* VI1_D8_G0_Y0 */
2848 [13] = RCAR_GP_PIN(5, 13), /* VI1_D9_G1_Y1 */
2849 [14] = RCAR_GP_PIN(5, 14), /* VI1_D10_G2_Y2 */
2850 [15] = RCAR_GP_PIN(5, 15), /* VI1_D11_G3_Y3 */
2851 [16] = RCAR_GP_PIN(5, 16), /* VI1_FIELD */
2852 [17] = SH_PFC_PIN_NONE,
2853 [18] = SH_PFC_PIN_NONE,
2854 [19] = SH_PFC_PIN_NONE,
2855 [20] = SH_PFC_PIN_NONE,
2856 [21] = SH_PFC_PIN_NONE,
2857 [22] = SH_PFC_PIN_NONE,
2858 [23] = SH_PFC_PIN_NONE,
2859 [24] = SH_PFC_PIN_NONE,
2860 [25] = SH_PFC_PIN_NONE,
2861 [26] = SH_PFC_PIN_NONE,
2862 [27] = SH_PFC_PIN_NONE,
2863 [28] = SH_PFC_PIN_NONE,
2864 [29] = SH_PFC_PIN_NONE,
2865 [30] = SH_PFC_PIN_NONE,
2866 [31] = SH_PFC_PIN_NONE,
2867 } },
2868 { PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) {
2869 [ 0] = RCAR_GP_PIN(6, 0), /* VI2_CLK */
2870 [ 1] = RCAR_GP_PIN(6, 1), /* VI2_CLKENB */
2871 [ 2] = RCAR_GP_PIN(6, 2), /* VI2_HSYNC# */
2872 [ 3] = RCAR_GP_PIN(6, 3), /* VI2_VSYNC# */
2873 [ 4] = RCAR_GP_PIN(6, 4), /* VI2_D0_C0 */
2874 [ 5] = RCAR_GP_PIN(6, 5), /* VI2_D1_C1 */
2875 [ 6] = RCAR_GP_PIN(6, 6), /* VI2_D2_C2 */
2876 [ 7] = RCAR_GP_PIN(6, 7), /* VI2_D3_C3 */
2877 [ 8] = RCAR_GP_PIN(6, 8), /* VI2_D4_C4 */
2878 [ 9] = RCAR_GP_PIN(6, 9), /* VI2_D5_C5 */
2879 [10] = RCAR_GP_PIN(6, 10), /* VI2_D6_C6 */
2880 [11] = RCAR_GP_PIN(6, 11), /* VI2_D7_C7 */
2881 [12] = RCAR_GP_PIN(6, 12), /* VI2_D8_Y0 */
2882 [13] = RCAR_GP_PIN(6, 13), /* VI2_D9_Y1 */
2883 [14] = RCAR_GP_PIN(6, 14), /* VI2_D10_Y2 */
2884 [15] = RCAR_GP_PIN(6, 15), /* VI2_D11_Y3 */
2885 [16] = RCAR_GP_PIN(6, 16), /* VI2_FIELD */
2886 [17] = SH_PFC_PIN_NONE,
2887 [18] = SH_PFC_PIN_NONE,
2888 [19] = SH_PFC_PIN_NONE,
2889 [20] = SH_PFC_PIN_NONE,
2890 [21] = SH_PFC_PIN_NONE,
2891 [22] = SH_PFC_PIN_NONE,
2892 [23] = SH_PFC_PIN_NONE,
2893 [24] = SH_PFC_PIN_NONE,
2894 [25] = SH_PFC_PIN_NONE,
2895 [26] = SH_PFC_PIN_NONE,
2896 [27] = SH_PFC_PIN_NONE,
2897 [28] = SH_PFC_PIN_NONE,
2898 [29] = SH_PFC_PIN_NONE,
2899 [30] = SH_PFC_PIN_NONE,
2900 [31] = SH_PFC_PIN_NONE,
2901 } },
2902 { PINMUX_BIAS_REG("PUPR7", 0xe606011c, "N/A", 0) {
2903 [ 0] = RCAR_GP_PIN(7, 0), /* VI3_CLK */
2904 [ 1] = RCAR_GP_PIN(7, 1), /* VI3_CLKENB */
2905 [ 2] = RCAR_GP_PIN(7, 2), /* VI3_HSYNC# */
2906 [ 3] = RCAR_GP_PIN(7, 3), /* VI3_VSYNC# */
2907 [ 4] = RCAR_GP_PIN(7, 4), /* VI3_D0_C0 */
2908 [ 5] = RCAR_GP_PIN(7, 5), /* VI3_D1_C1 */
2909 [ 6] = RCAR_GP_PIN(7, 6), /* VI3_D2_C2 */
2910 [ 7] = RCAR_GP_PIN(7, 7), /* VI3_D3_C3 */
2911 [ 8] = RCAR_GP_PIN(7, 8), /* VI3_D4_C4 */
2912 [ 9] = RCAR_GP_PIN(7, 9), /* VI3_D5_C5 */
2913 [10] = RCAR_GP_PIN(7, 10), /* VI3_D6_C6 */
2914 [11] = RCAR_GP_PIN(7, 11), /* VI3_D7_C7 */
2915 [12] = RCAR_GP_PIN(7, 12), /* VI3_D8_Y0 */
2916 [13] = RCAR_GP_PIN(7, 13), /* VI3_D9_Y1 */
2917 [14] = RCAR_GP_PIN(7, 14), /* VI3_D10_Y2 */
2918 [15] = RCAR_GP_PIN(7, 15), /* VI3_D11_Y3 */
2919 [16] = RCAR_GP_PIN(7, 16), /* VI3_FIELD */
2920 [17] = SH_PFC_PIN_NONE,
2921 [18] = SH_PFC_PIN_NONE,
2922 [19] = SH_PFC_PIN_NONE,
2923 [20] = SH_PFC_PIN_NONE,
2924 [21] = SH_PFC_PIN_NONE,
2925 [22] = SH_PFC_PIN_NONE,
2926 [23] = SH_PFC_PIN_NONE,
2927 [24] = SH_PFC_PIN_NONE,
2928 [25] = SH_PFC_PIN_NONE,
2929 [26] = SH_PFC_PIN_NONE,
2930 [27] = SH_PFC_PIN_NONE,
2931 [28] = SH_PFC_PIN_NONE,
2932 [29] = SH_PFC_PIN_NONE,
2933 [30] = SH_PFC_PIN_NONE,
2934 [31] = SH_PFC_PIN_NONE,
2935 } },
2936 { PINMUX_BIAS_REG("PUPR8", 0xe6060120, "N/A", 0) {
2937 [ 0] = RCAR_GP_PIN(8, 0), /* VI4_CLK */
2938 [ 1] = RCAR_GP_PIN(8, 1), /* VI4_CLKENB */
2939 [ 2] = RCAR_GP_PIN(8, 2), /* VI4_HSYNC# */
2940 [ 3] = RCAR_GP_PIN(8, 3), /* VI4_VSYNC# */
2941 [ 4] = RCAR_GP_PIN(8, 4), /* VI4_D0_C0 */
2942 [ 5] = RCAR_GP_PIN(8, 5), /* VI4_D1_C1 */
2943 [ 6] = RCAR_GP_PIN(8, 6), /* VI4_D2_C2 */
2944 [ 7] = RCAR_GP_PIN(8, 7), /* VI4_D3_C3 */
2945 [ 8] = RCAR_GP_PIN(8, 8), /* VI4_D4_C4 */
2946 [ 9] = RCAR_GP_PIN(8, 9), /* VI4_D5_C5 */
2947 [10] = RCAR_GP_PIN(8, 10), /* VI4_D6_C6 */
2948 [11] = RCAR_GP_PIN(8, 11), /* VI4_D7_C7 */
2949 [12] = RCAR_GP_PIN(8, 12), /* VI4_D8_Y0 */
2950 [13] = RCAR_GP_PIN(8, 13), /* VI4_D9_Y1 */
2951 [14] = RCAR_GP_PIN(8, 14), /* VI4_D10_Y2 */
2952 [15] = RCAR_GP_PIN(8, 15), /* VI4_D11_Y3 */
2953 [16] = RCAR_GP_PIN(8, 16), /* VI4_FIELD */
2954 [17] = SH_PFC_PIN_NONE,
2955 [18] = SH_PFC_PIN_NONE,
2956 [19] = SH_PFC_PIN_NONE,
2957 [20] = SH_PFC_PIN_NONE,
2958 [21] = SH_PFC_PIN_NONE,
2959 [22] = SH_PFC_PIN_NONE,
2960 [23] = SH_PFC_PIN_NONE,
2961 [24] = SH_PFC_PIN_NONE,
2962 [25] = SH_PFC_PIN_NONE,
2963 [26] = SH_PFC_PIN_NONE,
2964 [27] = SH_PFC_PIN_NONE,
2965 [28] = SH_PFC_PIN_NONE,
2966 [29] = SH_PFC_PIN_NONE,
2967 [30] = SH_PFC_PIN_NONE,
2968 [31] = SH_PFC_PIN_NONE,
2969 } },
2970 { PINMUX_BIAS_REG("PUPR9", 0xe6060124, "N/A", 0) {
2971 [ 0] = RCAR_GP_PIN(9, 0), /* VI5_CLK */
2972 [ 1] = RCAR_GP_PIN(9, 1), /* VI5_CLKENB */
2973 [ 2] = RCAR_GP_PIN(9, 2), /* VI5_HSYNC# */
2974 [ 3] = RCAR_GP_PIN(9, 3), /* VI5_VSYNC# */
2975 [ 4] = RCAR_GP_PIN(9, 4), /* VI5_D0_C0 */
2976 [ 5] = RCAR_GP_PIN(9, 5), /* VI5_D1_C1 */
2977 [ 6] = RCAR_GP_PIN(9, 6), /* VI5_D2_C2 */
2978 [ 7] = RCAR_GP_PIN(9, 7), /* VI5_D3_C3 */
2979 [ 8] = RCAR_GP_PIN(9, 8), /* VI5_D4_C4 */
2980 [ 9] = RCAR_GP_PIN(9, 9), /* VI5_D5_C5 */
2981 [10] = RCAR_GP_PIN(9, 10), /* VI5_D6_C6 */
2982 [11] = RCAR_GP_PIN(9, 11), /* VI5_D7_C7 */
2983 [12] = RCAR_GP_PIN(9, 12), /* VI5_D8_Y0 */
2984 [13] = RCAR_GP_PIN(9, 13), /* VI5_D9_Y1 */
2985 [14] = RCAR_GP_PIN(9, 14), /* VI5_D10_Y2 */
2986 [15] = RCAR_GP_PIN(9, 15), /* VI5_D11_Y3 */
2987 [16] = RCAR_GP_PIN(9, 16), /* VI5_FIELD */
2988 [17] = SH_PFC_PIN_NONE,
2989 [18] = SH_PFC_PIN_NONE,
2990 [19] = SH_PFC_PIN_NONE,
2991 [20] = SH_PFC_PIN_NONE,
2992 [21] = SH_PFC_PIN_NONE,
2993 [22] = SH_PFC_PIN_NONE,
2994 [23] = SH_PFC_PIN_NONE,
2995 [24] = SH_PFC_PIN_NONE,
2996 [25] = SH_PFC_PIN_NONE,
2997 [26] = SH_PFC_PIN_NONE,
2998 [27] = SH_PFC_PIN_NONE,
2999 [28] = SH_PFC_PIN_NONE,
3000 [29] = SH_PFC_PIN_NONE,
3001 [30] = SH_PFC_PIN_NONE,
3002 [31] = SH_PFC_PIN_NONE,
3003 } },
3004 { PINMUX_BIAS_REG("PUPR10", 0xe6060128, "N/A", 0) {
3005 [ 0] = RCAR_GP_PIN(10, 0), /* HSCK0 */
3006 [ 1] = RCAR_GP_PIN(10, 1), /* HCTS0# */
3007 [ 2] = RCAR_GP_PIN(10, 2), /* HRTS0# */
3008 [ 3] = RCAR_GP_PIN(10, 3), /* HTX0 */
3009 [ 4] = RCAR_GP_PIN(10, 4), /* HRX0 */
3010 [ 5] = RCAR_GP_PIN(10, 5), /* HSCK1 */
3011 [ 6] = RCAR_GP_PIN(10, 6), /* HRTS1# */
3012 [ 7] = RCAR_GP_PIN(10, 7), /* HCTS1# */
3013 [ 8] = RCAR_GP_PIN(10, 8), /* HTX1 */
3014 [ 9] = RCAR_GP_PIN(10, 9), /* HRX1 */
3015 [10] = RCAR_GP_PIN(10, 10), /* SCK0 */
3016 [11] = RCAR_GP_PIN(10, 11), /* CTS0# */
3017 [12] = RCAR_GP_PIN(10, 12), /* RTS0# */
3018 [13] = RCAR_GP_PIN(10, 13), /* TX0 */
3019 [14] = RCAR_GP_PIN(10, 14), /* RX0 */
3020 [15] = RCAR_GP_PIN(10, 15), /* SCK1 */
3021 [16] = RCAR_GP_PIN(10, 16), /* CTS1# */
3022 [17] = RCAR_GP_PIN(10, 17), /* RTS1# */
3023 [18] = RCAR_GP_PIN(10, 18), /* TX1 */
3024 [19] = RCAR_GP_PIN(10, 19), /* RX1 */
3025 [20] = RCAR_GP_PIN(10, 20), /* SCK2 */
3026 [21] = RCAR_GP_PIN(10, 21), /* TX2 */
3027 [22] = RCAR_GP_PIN(10, 22), /* RX2 */
3028 [23] = RCAR_GP_PIN(10, 23), /* SCK3 */
3029 [24] = RCAR_GP_PIN(10, 24), /* TX3 */
3030 [25] = RCAR_GP_PIN(10, 25), /* RX3 */
3031 [26] = RCAR_GP_PIN(10, 26), /* SCIF_CLK */
3032 [27] = RCAR_GP_PIN(10, 27), /* CAN0_TX */
3033 [28] = RCAR_GP_PIN(10, 28), /* CAN0_RX */
3034 [29] = RCAR_GP_PIN(10, 29), /* CAN_CLK */
3035 [30] = RCAR_GP_PIN(10, 30), /* CAN1_TX */
3036 [31] = RCAR_GP_PIN(10, 31), /* CAN1_RX */
3037 } },
3038 { PINMUX_BIAS_REG("PUPR11", 0xe606012c, "N/A", 0) {
3039 [ 0] = RCAR_GP_PIN(11, 0), /* PWM0 */
3040 [ 1] = RCAR_GP_PIN(11, 1), /* PWM1 */
3041 [ 2] = RCAR_GP_PIN(11, 2), /* PWM2 */
3042 [ 3] = RCAR_GP_PIN(11, 3), /* PWM3 */
3043 [ 4] = RCAR_GP_PIN(11, 4), /* PWM4 */
3044 [ 5] = RCAR_GP_PIN(11, 5), /* SD0_CLK */
3045 [ 6] = RCAR_GP_PIN(11, 6), /* SD0_CMD */
3046 [ 7] = RCAR_GP_PIN(11, 7), /* SD0_DAT0 */
3047 [ 8] = RCAR_GP_PIN(11, 8), /* SD0_DAT1 */
3048 [ 9] = RCAR_GP_PIN(11, 9), /* SD0_DAT2 */
3049 [10] = RCAR_GP_PIN(11, 10), /* SD0_DAT3 */
3050 [11] = RCAR_GP_PIN(11, 11), /* SD0_CD */
3051 [12] = RCAR_GP_PIN(11, 12), /* SD0_WP */
3052 [13] = RCAR_GP_PIN(11, 13), /* SSI_SCK3 */
3053 [14] = RCAR_GP_PIN(11, 14), /* SSI_WS3 */
3054 [15] = RCAR_GP_PIN(11, 15), /* SSI_SDATA3 */
3055 [16] = RCAR_GP_PIN(11, 16), /* SSI_SCK4 */
3056 [17] = RCAR_GP_PIN(11, 17), /* SSI_WS4 */
3057 [18] = RCAR_GP_PIN(11, 18), /* SSI_SDATA4 */
3058 [19] = RCAR_GP_PIN(11, 19), /* AUDIO_CLKOUT */
3059 [20] = RCAR_GP_PIN(11, 20), /* AUDIO_CLKA */
3060 [21] = RCAR_GP_PIN(11, 21), /* AUDIO_CLKB */
3061 [22] = RCAR_GP_PIN(11, 22), /* ADICLK */
3062 [23] = RCAR_GP_PIN(11, 23), /* ADICS_SAMP */
3063 [24] = RCAR_GP_PIN(11, 24), /* ADIDATA */
3064 [25] = RCAR_GP_PIN(11, 25), /* ADICHS0 */
3065 [26] = RCAR_GP_PIN(11, 26), /* ADICHS1 */
3066 [27] = RCAR_GP_PIN(11, 27), /* ADICHS2 */
3067 [28] = RCAR_GP_PIN(11, 28), /* AVS1 */
3068 [29] = RCAR_GP_PIN(11, 29), /* AVS2 */
3069 [30] = SH_PFC_PIN_NONE,
3070 [31] = SH_PFC_PIN_NONE,
3071 } },
3072 { PINMUX_BIAS_REG("PUPR12", 0xe6060130, "N/A", 0) {
3073 /* PUPR12 pull-up pins */
3074 [ 0] = PIN_DU0_DOTCLKIN, /* DU0_DOTCLKIN */
3075 [ 1] = PIN_DU0_DOTCLKOUT, /* DU0_DOTCLKOUT */
3076 [ 2] = PIN_DU1_DOTCLKIN, /* DU1_DOTCLKIN */
3077 [ 3] = PIN_DU1_DOTCLKOUT, /* DU1_DOTCLKOUT */
3078 [ 4] = PIN_TRST_N, /* TRST# */
3079 [ 5] = PIN_TCK, /* TCK */
3080 [ 6] = PIN_TMS, /* TMS */
3081 [ 7] = PIN_TDI, /* TDI */
3082 [ 8] = SH_PFC_PIN_NONE,
3083 [ 9] = SH_PFC_PIN_NONE,
3084 [10] = SH_PFC_PIN_NONE,
3085 [11] = SH_PFC_PIN_NONE,
3086 [12] = SH_PFC_PIN_NONE,
3087 [13] = SH_PFC_PIN_NONE,
3088 [14] = SH_PFC_PIN_NONE,
3089 [15] = SH_PFC_PIN_NONE,
3090 [16] = SH_PFC_PIN_NONE,
3091 [17] = SH_PFC_PIN_NONE,
3092 [18] = SH_PFC_PIN_NONE,
3093 [19] = SH_PFC_PIN_NONE,
3094 [20] = SH_PFC_PIN_NONE,
3095 [21] = SH_PFC_PIN_NONE,
3096 [22] = SH_PFC_PIN_NONE,
3097 [23] = SH_PFC_PIN_NONE,
3098 [24] = SH_PFC_PIN_NONE,
3099 [25] = SH_PFC_PIN_NONE,
3100 [26] = SH_PFC_PIN_NONE,
3101 [27] = SH_PFC_PIN_NONE,
3102 [28] = SH_PFC_PIN_NONE,
3103 [29] = SH_PFC_PIN_NONE,
3104 [30] = SH_PFC_PIN_NONE,
3105 [31] = SH_PFC_PIN_NONE,
3106 } },
3107 { PINMUX_BIAS_REG("N/A", 0, "PUPR12", 0xe6060130) {
3108 /* PUPR12 pull-down pins */
3109 [ 0] = SH_PFC_PIN_NONE,
3110 [ 1] = SH_PFC_PIN_NONE,
3111 [ 2] = SH_PFC_PIN_NONE,
3112 [ 3] = SH_PFC_PIN_NONE,
3113 [ 4] = SH_PFC_PIN_NONE,
3114 [ 5] = SH_PFC_PIN_NONE,
3115 [ 6] = SH_PFC_PIN_NONE,
3116 [ 7] = SH_PFC_PIN_NONE,
3117 [ 8] = PIN_EDBGREQ, /* EDBGREQ */
3118 [ 9] = SH_PFC_PIN_NONE,
3119 [10] = SH_PFC_PIN_NONE,
3120 [11] = SH_PFC_PIN_NONE,
3121 [12] = SH_PFC_PIN_NONE,
3122 [13] = SH_PFC_PIN_NONE,
3123 [14] = SH_PFC_PIN_NONE,
3124 [15] = SH_PFC_PIN_NONE,
3125 [16] = SH_PFC_PIN_NONE,
3126 [17] = SH_PFC_PIN_NONE,
3127 [18] = SH_PFC_PIN_NONE,
3128 [19] = SH_PFC_PIN_NONE,
3129 [20] = SH_PFC_PIN_NONE,
3130 [21] = SH_PFC_PIN_NONE,
3131 [22] = SH_PFC_PIN_NONE,
3132 [23] = SH_PFC_PIN_NONE,
3133 [24] = SH_PFC_PIN_NONE,
3134 [25] = SH_PFC_PIN_NONE,
3135 [26] = SH_PFC_PIN_NONE,
3136 [27] = SH_PFC_PIN_NONE,
3137 [28] = SH_PFC_PIN_NONE,
3138 [29] = SH_PFC_PIN_NONE,
3139 [30] = SH_PFC_PIN_NONE,
3140 [31] = SH_PFC_PIN_NONE,
3141 } },
3142 { /* sentinel */ }
3143};
3144
3145static const struct sh_pfc_soc_operations r8a7792_pfc_ops = {
3146 .get_bias = rcar_pinmux_get_bias,
3147 .set_bias = rcar_pinmux_set_bias,
3148};
3149
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]3150const struct sh_pfc_soc_info r8a7792_pinmux_info = {
3151 .name = "r8a77920_pfc",
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]3152 .ops = &r8a7792_pfc_ops,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]3153 .unlock_reg = 0xe6060000, /* PMMR */
3154
3155 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3156
3157 .pins = pinmux_pins,
3158 .nr_pins = ARRAY_SIZE(pinmux_pins),
3159 .groups = pinmux_groups,
3160 .nr_groups = ARRAY_SIZE(pinmux_groups),
3161 .functions = pinmux_functions,
3162 .nr_functions = ARRAY_SIZE(pinmux_functions),
3163
3164 .cfg_regs = pinmux_config_regs,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]3165 .bias_regs = pinmux_bias_regs,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]3166
3167 .pinmux_data = pinmux_data,
3168 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
3169};