| Neil Armstrong | 16f3929 | 2024-11-25 09:54:24 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (c) 2023, Linaro Limited |
| 4 | */ |
| 5 | |
| 6 | #ifndef QCOM_PHY_QMP_PCS_PCIE_V6_20_H_ |
| 7 | #define QCOM_PHY_QMP_PCS_PCIE_V6_20_H_ |
| 8 | |
| 9 | /* Only for QMP V6_20 PHY - PCIE have different offsets than V5 */ |
| 10 | #define QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2 0x00c |
| 11 | #define QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG 0x018 |
| 12 | #define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE 0x01c |
| 13 | #define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS 0x090 |
| 14 | #define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1 0x0a0 |
| 15 | #define QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME 0x0f0 |
| 16 | #define QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME 0x0f4 |
| 17 | #define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5 0x108 |
| 18 | #define QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN 0x15c |
| 19 | #define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1 0x17c |
| 20 | #define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3 0x184 |
| 21 | #define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5 0x18c |
| 22 | #define QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5 0x1ac |
| 23 | #define QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5 0x1c0 |
| 24 | |
| 25 | #endif |