| Yanhong Wang | 94817bf | 2023-03-29 11:42:22 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 OR MIT |
| 2 | /* |
| 3 | * Copyright (C) 2022 StarFive Technology Co., Ltd. |
| 4 | */ |
| 5 | |
| 6 | #include <dt-bindings/reset/starfive,jh7110-crg.h> |
| 7 | |
| 8 | / { |
| 9 | cpus: cpus { |
| 10 | bootph-pre-ram; |
| 11 | |
| 12 | S7_0: cpu@0 { |
| 13 | bootph-pre-ram; |
| 14 | status = "okay"; |
| 15 | cpu0_intc: interrupt-controller { |
| 16 | bootph-pre-ram; |
| 17 | }; |
| 18 | }; |
| 19 | |
| 20 | U74_1: cpu@1 { |
| 21 | bootph-pre-ram; |
| 22 | cpu1_intc: interrupt-controller { |
| 23 | bootph-pre-ram; |
| 24 | }; |
| 25 | }; |
| 26 | |
| 27 | U74_2: cpu@2 { |
| 28 | bootph-pre-ram; |
| 29 | cpu2_intc: interrupt-controller { |
| 30 | bootph-pre-ram; |
| 31 | }; |
| 32 | }; |
| 33 | |
| 34 | U74_3: cpu@3 { |
| 35 | bootph-pre-ram; |
| 36 | cpu3_intc: interrupt-controller { |
| 37 | bootph-pre-ram; |
| 38 | }; |
| 39 | }; |
| 40 | |
| 41 | U74_4: cpu@4 { |
| 42 | bootph-pre-ram; |
| 43 | cpu4_intc: interrupt-controller { |
| 44 | bootph-pre-ram; |
| 45 | }; |
| 46 | }; |
| 47 | }; |
| 48 | |
| Hal Feng | 7cbf1a4 | 2024-12-08 17:19:32 +0800 | [diff] [blame] | 49 | timer { |
| 50 | compatible = "riscv,timer"; |
| 51 | interrupts-extended = <&cpu0_intc 5>, |
| 52 | <&cpu1_intc 5>, |
| 53 | <&cpu2_intc 5>, |
| 54 | <&cpu3_intc 5>, |
| 55 | <&cpu4_intc 5>; |
| 56 | }; |
| 57 | |
| Yanhong Wang | 94817bf | 2023-03-29 11:42:22 +0800 | [diff] [blame] | 58 | soc { |
| 59 | bootph-pre-ram; |
| 60 | |
| 61 | clint: timer@2000000 { |
| 62 | bootph-pre-ram; |
| 63 | }; |
| 64 | |
| 65 | dmc: dmc@15700000 { |
| 66 | bootph-pre-ram; |
| 67 | compatible = "starfive,jh7110-dmc"; |
| 68 | reg = <0x0 0x15700000 0x0 0x10000>, |
| 69 | <0x0 0x13000000 0x0 0x10000>; |
| 70 | resets = <&syscrg JH7110_SYSRST_DDR_AXI>, |
| 71 | <&syscrg JH7110_SYSRST_DDR_OSC>, |
| 72 | <&syscrg JH7110_SYSRST_DDR_APB>; |
| 73 | reset-names = "axi", "osc", "apb"; |
| Hal Feng | 8f4577e | 2024-12-08 17:19:31 +0800 | [diff] [blame] | 74 | clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; |
| Yanhong Wang | 94817bf | 2023-03-29 11:42:22 +0800 | [diff] [blame] | 75 | clock-names = "pll1_out"; |
| 76 | clock-frequency = <2133>; |
| 77 | }; |
| 78 | }; |
| 79 | }; |
| 80 | |
| 81 | &osc { |
| 82 | bootph-pre-ram; |
| 83 | }; |
| 84 | |
| Hal Feng | 7cbf1a4 | 2024-12-08 17:19:32 +0800 | [diff] [blame] | 85 | &gmac0_rgmii_rxin { |
| 86 | bootph-pre-ram; |
| 87 | }; |
| 88 | |
| Yanhong Wang | 94817bf | 2023-03-29 11:42:22 +0800 | [diff] [blame] | 89 | &gmac0_rmii_refin { |
| 90 | bootph-pre-ram; |
| 91 | }; |
| 92 | |
| Hal Feng | 7cbf1a4 | 2024-12-08 17:19:32 +0800 | [diff] [blame] | 93 | &gmac1_rgmii_rxin { |
| 94 | bootph-pre-ram; |
| 95 | }; |
| 96 | |
| 97 | &gmac1_rmii_refin { |
| 98 | bootph-pre-ram; |
| 99 | }; |
| 100 | |
| Yanhong Wang | 94817bf | 2023-03-29 11:42:22 +0800 | [diff] [blame] | 101 | &aoncrg { |
| 102 | bootph-pre-ram; |
| 103 | }; |
| 104 | |
| 105 | &syscrg { |
| 106 | bootph-pre-ram; |
| Yanhong Wang | 94817bf | 2023-03-29 11:42:22 +0800 | [diff] [blame] | 107 | }; |
| 108 | |
| 109 | &stgcrg { |
| 110 | bootph-pre-ram; |
| 111 | }; |
| 112 | |
| 113 | &sys_syscon { |
| 114 | bootph-pre-ram; |
| 115 | }; |