| Duje Mihanović | ba441f5 | 2025-01-24 16:47:49 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | /dts-v1/; |
| 3 | |
| 4 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 5 | |
| 6 | / { |
| 7 | model = "Marvell Armada PXA1908"; |
| 8 | compatible = "marvell,pxa1908"; |
| 9 | #address-cells = <2>; |
| 10 | #size-cells = <2>; |
| 11 | interrupt-parent = <&gic>; |
| 12 | |
| 13 | cpus { |
| 14 | #address-cells = <2>; |
| 15 | #size-cells = <0>; |
| 16 | |
| 17 | cpu0: cpu@0 { |
| 18 | device_type = "cpu"; |
| 19 | compatible = "arm,cortex-a53"; |
| 20 | reg = <0 0>; |
| 21 | enable-method = "psci"; |
| 22 | }; |
| 23 | |
| 24 | cpu1: cpu@1 { |
| 25 | device_type = "cpu"; |
| 26 | compatible = "arm,cortex-a53"; |
| 27 | reg = <0 1>; |
| 28 | enable-method = "psci"; |
| 29 | }; |
| 30 | |
| 31 | cpu2: cpu@2 { |
| 32 | device_type = "cpu"; |
| 33 | compatible = "arm,cortex-a53"; |
| 34 | reg = <0 2>; |
| 35 | enable-method = "psci"; |
| 36 | }; |
| 37 | |
| 38 | cpu3: cpu@3 { |
| 39 | device_type = "cpu"; |
| 40 | compatible = "arm,cortex-a53"; |
| 41 | reg = <0 3>; |
| 42 | enable-method = "psci"; |
| 43 | }; |
| 44 | }; |
| 45 | |
| 46 | psci { |
| 47 | compatible = "arm,psci-0.2"; |
| 48 | method = "smc"; |
| 49 | }; |
| 50 | |
| 51 | timer { |
| 52 | compatible = "arm,armv8-timer"; |
| 53 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 54 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 55 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 56 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| 57 | }; |
| 58 | |
| 59 | soc { |
| 60 | compatible = "simple-bus"; |
| 61 | #address-cells = <2>; |
| 62 | #size-cells = <2>; |
| 63 | ranges; |
| 64 | |
| 65 | gic: interrupt-controller@d1df9000 { |
| 66 | compatible = "arm,gic-400"; |
| 67 | reg = <0 0xd1df9000 0 0x1000>, |
| 68 | <0 0xd1dfa000 0 0x2000>, |
| 69 | /* The subsequent registers are guesses. */ |
| 70 | <0 0xd1dfc000 0 0x2000>, |
| 71 | <0 0xd1dfe000 0 0x2000>; |
| 72 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| 73 | interrupt-controller; |
| 74 | #interrupt-cells = <3>; |
| 75 | }; |
| 76 | |
| 77 | apb@d4000000 { |
| 78 | compatible = "simple-bus"; |
| 79 | reg = <0 0xd4000000 0 0x200000>; |
| 80 | #address-cells = <1>; |
| 81 | #size-cells = <1>; |
| 82 | ranges = <0 0 0xd4000000 0x200000>; |
| 83 | |
| 84 | uart0: serial@17000 { |
| 85 | compatible = "mrvl,mmp-uart", "intel,xscale-uart"; |
| 86 | reg = <0x17000 0x1000>; |
| 87 | clock-frequency = <14745600>; |
| 88 | reg-shift = <2>; |
| 89 | }; |
| 90 | |
| 91 | uart1: serial@18000 { |
| 92 | compatible = "mrvl,mmp-uart", "intel,xscale-uart"; |
| 93 | reg = <0x18000 0x1000>; |
| 94 | clock-frequency = <14745600>; |
| 95 | reg-shift = <2>; |
| 96 | }; |
| 97 | |
| 98 | uart2: serial@36000 { |
| 99 | compatible = "mrvl,mmp-uart", "intel,xscale-uart"; |
| 100 | reg = <0x36000 0x1000>; |
| 101 | clock-frequency = <117000000>; |
| 102 | reg-shift = <2>; |
| 103 | }; |
| 104 | }; |
| 105 | }; |
| 106 | }; |