| developer | 2de1f36 | 2025-01-23 16:55:01 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | /* |
| 3 | * Copyright (C) 2023 MediaTek Inc. |
| 4 | * Author: Sam.Shih <sam.shih@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | #include "mt7987.dtsi" |
| 9 | #include "mt7987-pinctrl.dtsi" |
| 10 | |
| 11 | / { |
| 12 | compatible = "mediatek,mt7987a", "mediatek,mt7987"; |
| 13 | |
| 14 | memory { |
| 15 | reg = <0 0x40000000 0 0x10000000>; |
| 16 | }; |
| 17 | |
| 18 | }; |
| 19 | |
| 20 | &afe { |
| 21 | pinctrl-names = "default"; |
| 22 | pinctrl-0 = <&pcm_pins>; |
| 23 | status = "okay"; |
| 24 | }; |
| 25 | |
| 26 | &boottrap { |
| 27 | status = "okay"; |
| 28 | }; |
| 29 | |
| 30 | &fan { |
| 31 | pwms = <&pwm 0 50000 0>; |
| 32 | status = "okay"; |
| 33 | }; |
| 34 | |
| 35 | &i2c0 { |
| 36 | pinctrl-names = "default"; |
| 37 | pinctrl-0 = <&i2c0_pins>; |
| 38 | status = "okay"; |
| 39 | }; |
| 40 | |
| 41 | &infra_bus_prot { |
| 42 | status = "okay"; |
| 43 | }; |
| 44 | |
| 45 | &lvts { |
| 46 | status = "okay"; |
| 47 | }; |
| 48 | |
| 49 | &pcie0 { |
| 50 | pinctrl-names = "default"; |
| 51 | pinctrl-0 = <&pcie0_pins>; |
| 52 | status = "okay"; |
| 53 | }; |
| 54 | |
| 55 | &pcie1 { |
| 56 | pinctrl-names = "default"; |
| 57 | pinctrl-0 = <&pcie1_pins>; |
| 58 | status = "disabled"; |
| 59 | }; |
| 60 | |
| 61 | &pwm { |
| 62 | status = "okay"; |
| 63 | }; |
| 64 | |
| 65 | &spi1 { |
| 66 | pinctrl-names = "default"; |
| 67 | pinctrl-0 = <&spic_pins>; |
| 68 | status = "okay"; |
| 69 | }; |
| 70 | |
| 71 | &trng { |
| 72 | status = "okay"; |
| 73 | }; |
| 74 | |
| 75 | &uart0 { |
| 76 | status = "okay"; |
| 77 | }; |
| 78 | |
| 79 | &watchdog { |
| 80 | status = "okay"; |
| 81 | }; |
| 82 | |
| 83 | &xhci { |
| 84 | mediatek,u3p-dis-msk = <0x00000001>; |
| 85 | phys = <&tphyu2port0 PHY_TYPE_USB2>; |
| 86 | |
| 87 | clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>, |
| 88 | <&infracfg CLK_INFRA_USB_XHCI_CK_P1>, |
| 89 | <&infracfg CLK_INFRA_USB_CK_P1>, |
| 90 | <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>, |
| 91 | <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>; |
| 92 | clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck", |
| 93 | "dma_ck"; |
| 94 | |
| 95 | status = "okay"; |
| 96 | }; |