blob: b07e6da41e274d3a5a93fd77cc8492b52ad55580 [file] [log] [blame]
developer65907502025-01-23 16:55:05 +08001// SPDX-License-Identifier: GPL-2.0
2
3#include "mt7987a-u-boot.dtsi"
4#include "mt7987-netsys-u-boot.dtsi"
5
6/ {
7 model = "mt7987";
8 compatible = "mediatek,mt7987", "mediatek,mt7987-sd-rfb";
9};
10
11&eth0 {
12 status = "okay";
13 pinctrl-names = "default";
14 pinctrl-0 = <&mdio0_pins>;
15 phy-mode = "2500base-x";
16 mediatek,switch = "auto";
17 reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>;
18
19 fixed-link {
20 speed = <2500>;
21 full-duplex;
22 pause;
23 };
24};
25
26&mmc0 {
27 pinctrl-names = "default";
28 pinctrl-0 = <&sd_pins_default>;
29 max-frequency = <48000000>;
30 bus-width = <4>;
31 cap-sd-highspeed;
32 vmmc-supply = <&reg_3p3v>;
33 vqmmc-supply = <&reg_3p3v>;
34 status = "okay";
35};
36
37&spi2 {
38 pinctrl-names = "default";
39 pinctrl-0 = <&spi2_flash_pins>;
40 #address-cells = <1>;
41 #size-cells = <0>;
42 status = "okay";
43 must_tx;
44 enhance_timing;
45 dma_ext;
46 ipm_design;
47 support_quad;
48 tick_dly = <2>;
49 sample_sel = <0>;
50
51 /delete-node/ spi_nor@0;
52 spi_nor@0 {
53 compatible = "jedec,spi-nor";
54 reg = <0>;
55 spi-max-frequency = <52000000>;
56 spi-rx-bus-width = <4>;
57 spi-tx-bus-width = <4>;
58 };
59};