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git01.mediatek.com / filogic / uboot / bf7c0cee160adfa8cbea76491b51fb492d1bf9ba / . / arch / arm / dts / mt7987.dtsi
blob: fd1585f658d0543da1dc51f54ee8bb41a491c568 [file] [log] [blame]
developer2de1f362025-01-23 16:55:01 +0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2023 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/phy/phy.h>
10#include <dt-bindings/reset/ti-syscon.h>
11#include <dt-bindings/clock/mediatek,mt7987-clk.h>
12#include <dt-bindings/pinctrl/mt65xx.h>
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/thermal/thermal.h>
15#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
16
17/ {
18 compatible = "mediatek,mt7987";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
22
23 clkxtal: oscillator@0 {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <40000000>;
27 clock-output-names = "clkxtal";
28 };
29
30 vproc: regulator-vproc {
31 compatible = "regulator-fixed";
32 regulator-name = "proc";
33 regulator-min-microvolt = <8500000>;
34 regulator-max-microvolt = <8500000>;
35 regulator-boot-on;
36 regulator-always-on;
37 };
38
39 firmware {
40 optee {
41 method = "smc";
42 compatible = "linaro,optee-tz";
43 status = "okay";
44 };
45 };
46
47 cpus {
48 #address-cells = <1>;
49 #size-cells = <0>;
50 cpu0: cpu@0 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a53";
53 enable-method = "psci";
54 next-level-cache = <&l2_cache>;
55 reg = <0x0>;
56 clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
57 <&topckgen CLK_TOP_CB_CKSQ_40M>,
58 <&apmixedsys CLK_APMIXED_ARM_LL>;
59 clock-names = "cpu", "intermediate", "armpll";
60 operating-points-v2 = <&cluster0_opp>;
61 };
62
63 cpu1: cpu@1 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a53";
66 enable-method = "psci";
67 next-level-cache = <&l2_cache>;
68 reg = <0x1>;
69 clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
70 <&topckgen CLK_TOP_CB_CKSQ_40M>,
71 <&apmixedsys CLK_APMIXED_ARM_LL>;
72 clock-names = "cpu", "intermediate", "armpll";
73 operating-points-v2 = <&cluster0_opp>;
74 };
75
76 cpu2: cpu@2 {
77 device_type = "cpu";
78 compatible = "arm,cortex-a53";
79 enable-method = "psci";
80 next-level-cache = <&l2_cache>;
81 reg = <0x2>;
82 clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
83 <&topckgen CLK_TOP_CB_CKSQ_40M>,
84 <&apmixedsys CLK_APMIXED_ARM_LL>;
85 clock-names = "cpu", "intermediate", "armpll";
86 operating-points-v2 = <&cluster0_opp>;
87 };
88
89 cpu3: cpu@3 {
90 device_type = "cpu";
91 compatible = "arm,cortex-a53";
92 enable-method = "psci";
93 next-level-cache = <&l2_cache>;
94 reg = <0x3>;
95 clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
96 <&topckgen CLK_TOP_CB_CKSQ_40M>,
97 <&apmixedsys CLK_APMIXED_ARM_LL>;
98 clock-names = "cpu", "intermediate", "armpll";
99 operating-points-v2 = <&cluster0_opp>;
100 };
101
102 cluster0_opp: opp_table0 {
103 compatible = "operating-points-v2";
104 opp-shared;
105 opp00 {
106 opp-hz = /bits/ 64 <500000000>;
107 opp-microvolt = <850000>;
108 };
109 opp01 {
110 opp-hz = /bits/ 64 <1300000000>;
111 opp-microvolt = <850000>;
112 };
113 opp02 {
114 opp-hz = /bits/ 64 <1600000000>;
115 opp-microvolt = <850000>;
116 };
117 opp03 {
118 opp-hz = /bits/ 64 <2000000000>;
119 opp-microvolt = <850000>;
120 };
121 };
122
123 l2_cache: l2-cache {
124 compatible = "cache";
125 cache-level = <2>;
126 };
127 };
128
129 clk40m: clk40m {
130 compatible = "fixed-clock";
131 #clock-cells = <0>;
132 clock-frequency = <40000000>;
133 };
134
135 clkitg: clkitg {
136 compatible = "simple-bus";
137 status = "disabled";
138 };
139
140 clksys: soc_clksys {
141 #address-cells = <2>;
142 #size-cells = <2>;
143 compatible = "simple-bus";
144 ranges;
145
146 infracfg: infracfg@10001000 {
147 compatible = "mediatek,mt7987-infracfg", "syscon";
148 reg = <0 0x10001000 0 0x1000>;
149 #clock-cells = <1>;
150 };
151
152 topckgen: topckgen@1001b000 {
153 compatible = "mediatek,mt7987-topckgen", "syscon";
154 reg = <0 0x1001b000 0 0x1000>;
155 #clock-cells = <1>;
156 };
157
158 apmixedsys: apmixedsys@1001e000 {
159 compatible = "mediatek,mt7987-apmixedsys", "syscon";
160 reg = <0 0x1001e000 0 0x1000>;
161 #clock-cells = <1>;
162 };
163
164 sgmiisys0: syscon@10060000 {
165 compatible = "mediatek,mt7987-sgmiisys",
166 "mediatek,mt7987-sgmiisys_0",
167 "syscon";
168 reg = <0 0x10060000 0 0x1000>;
169 #clock-cells = <1>;
170 };
171
172 sgmiisys1: syscon@10070000 {
173 compatible = "mediatek,mt7987-sgmiisys",
174 "mediatek,mt7987-sgmiisys_1",
175 "syscon";
176 reg = <0 0x10070000 0 0x1000>;
177 #clock-cells = <1>;
178 };
179
180 mcusys: mcusys@10400000 {
181 compatible = "mediatek,mt7987-mcusys", "syscon";
182 reg = <0 0x10400000 0 0x1000>;
183 #clock-cells = <1>;
184 };
185
186 ethsys: syscon@15000000 {
187 #address-cells = <1>;
188 #size-cells = <1>;
189 compatible = "mediatek,mt7987-ethdma",
190 "mediatek,mt7987-ethsys",
191 "syscon";
192 reg = <0 0x15000000 0 0x1000>;
193 #clock-cells = <1>;
194 #reset-cells = <1>;
195 ethsysrst: reset-controller {
196 compatible = "ti,syscon-reset";
197 #reset-cells = <1>;
198 ti,reset-bits =
199 <0x34 4 0x34 4 0x34 4
200 (ASSERT_SET | DEASSERT_CLEAR |
201 STATUS_SET)>;
202 };
203 };
204 };
205
206 fan: pwm-fan {
207 compatible = "pwm-fan";
208 cooling-levels = <0 128 255>;
209 #cooling-cells = <2>;
210 #thermal-sensor-cells = <1>;
211 status = "disabled";
212 };
213
214 pmu: pmu {
215 compatible = "arm,cortex-a53-pmu";
216 interrupt-parent = <&gic>;
217 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
218 };
219
220 psci {
221 compatible = "arm,psci-0.2";
222 method = "smc";
223 };
224
225 reserved-memory {
226 #address-cells = <2>;
227 #size-cells = <2>;
228 ranges;
229
230 wmcpu_emi: wmcpu-reserved@50000000 {
231 compatible = "mediatek,wmcpu-reserved";
232 no-map;
233 reg = <0 0x50000000 0 0x00100000>;
234 };
235 };
236
237 thermal-zones {
238 thermal_zone0: soc_thermal {
239 polling-delay-passive = <1000>;
240 polling-delay = <1000>;
241 thermal-sensors = <&lvts 0>;
242 trips {
243 cpu_trip_crit: crit {
244 temperature = <125000>;
245 hysteresis = <2000>;
246 type = "critical";
247 };
248
249 cpu_trip_hot: hot {
250 temperature = <120000>;
251 hysteresis = <2000>;
252 type = "hot";
253 };
254
255 cpu_trip_active1: active1 {
256 temperature = <115000>;
257 hysteresis = <2000>;
258 type = "active";
259 };
260
261 cpu_trip_active0: active0 {
262 temperature = <85000>;
263 hysteresis = <2000>;
264 type = "active";
265 };
266
267 cpu_trip_passive: passive {
268 temperature = <40000>;
269 hysteresis = <2000>;
270 type = "passive";
271 };
272 };
273
274 cooling-maps {
275 cpu-active-high {
276 cooling-device = <&fan 2 2>;
277 trip = <&cpu_trip_active1>;
278 };
279
280 cpu-active-low {
281 cooling-device = <&fan 1 1>;
282 trip = <&cpu_trip_active0>;
283 };
284
285 cpu-passive {
286 cooling-device = <&fan 0 0>;
287 trip = <&cpu_trip_passive>;
288 };
289 };
290 };
291
292 thermal_zone1: mcusys_thermal {
293 polling-delay-passive = <1000>;
294 polling-delay = <1000>;
295 thermal-sensors = <&lvts 1>;
296 };
297
298 thermal_zone2: eth2p5g_thermal {
299 polling-delay-passive = <1000>;
300 polling-delay = <1000>;
301 thermal-sensors = <&lvts 2>;
302 };
303 };
304
305 timer {
306 compatible = "arm,armv8-timer";
307 interrupt-parent = <&gic>;
308 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
309 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
310 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
311 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
312 };
313
314 soc: soc {
315 #address-cells = <2>;
316 #size-cells = <2>;
317 compatible = "simple-bus";
318 ranges;
319
320 hwver: hwver@8000000 {
321 compatible = "mediatek,hwver", "syscon";
322 reg = <0 0x8000000 0 0x1000>;
323 };
324
325 gic: interrupt-controller@c000000 {
326 compatible = "arm,gic-v3";
327 #interrupt-cells = <3>;
328 interrupt-parent = <&gic>;
329 interrupt-controller;
330 reg = <0 0x0c000000 0 0x40000>, /* GICD */
331 <0 0x0c080000 0 0x200000>, /* GICR */
332 <0 0x0c400000 0 0x2000>, /* GICC */
333 <0 0x0c410000 0 0x1000>, /* GICH */
334 <0 0x0c420000 0 0x2000>; /* GICV */
335 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
336 };
337
338 infra_bus_prot: infra_bus_prot@1000310c {
339 compatible = "mediatek,infracfg_ao_bus_hang_prot";
340 reg = <0 0x1000310c 0 0x14>;
341 status = "disabled";
342 };
343
344 watchdog: watchdog@1001c000 {
345 compatible = "mediatek,mt7622-wdt",
346 "mediatek,mt6589-wdt",
347 "syscon";
348 reg = <0 0x1001c000 0 0x1000>;
349 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
350 #reset-cells = <1>;
351 status = "disabled";
352 };
353
354 pio: pinctrl@1001f000 {
355 compatible = "mediatek,mt7987-pinctrl";
356 reg = <0 0x1001f000 0 0x1000>,
357 <0 0x11d00000 0 0x1000>,
358 <0 0x11e00000 0 0x1000>,
359 <0 0x11f00000 0 0x1000>,
360 <0 0x11f40000 0 0x1000>,
361 <0 0x11f60000 0 0x1000>,
362 <0 0x1000b000 0 0x1000>;
363 reg-names = "gpio", "iocfg_rb", "iocfg_lb", "iocfg_rt1",
364 "iocfg_rt2", "iocfg_tl", "eint";
365 gpio-controller;
366 #gpio-cells = <2>;
367 gpio-ranges = <&pio 0 0 50>;
368 interrupt-controller;
369 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
370 interrupt-parent = <&gic>;
371 #interrupt-cells = <2>;
372
373 pcie1pereset {
374 gpio-hog;
375 gpios = <36 GPIO_ACTIVE_HIGH>;
376 output-high;
377 };
378 };
379
380 boottrap: boottrap@1001f6f0 {
381 compatible = "mediatek,boottrap";
382 reg = <0 0x1001f6f0 0 0x20>;
383 status = "disabled";
384 };
385
386 trng: trng@1020f000 {
387 compatible = "mediatek,mt7987-rng";
388 status = "disabled";
389 };
390
391 pwm: pwm@10048000 {
392 compatible = "mediatek,mt7988-pwm";
393 reg = <0 0x10048000 0 0x1000>;
394 #pwm-cells = <2>;
395 clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
396 <&infracfg CLK_INFRA_66M_PWM_HCK>,
397 <&clkxtal>,
398 <&clkxtal>,
399 <&clkxtal>,
400 <&clkxtal>,
401 <&clkxtal>,
402 <&clkxtal>,
403 <&clkxtal>,
404 <&clkxtal>;
405 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
406 "pwm4","pwm5","pwm6","pwm7","pwm8";
407 status = "disabled";
408 };
409
410 uart0: serial@11000000 {
411 compatible = "mediatek,mt7986-uart",
412 "mediatek,mt6577-uart";
413 reg = <0 0x11000000 0 0x100>;
414 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&infracfg CLK_INFRA_52M_UART0_CK>,
416 <&infracfg CLK_INFRA_66M_UART0_PCK>;
417 clock-names = "baud", "bus";
418 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
419 <&infracfg CLK_INFRA_MUX_UART0_SEL>;
420 assigned-clock-parents = <&topckgen
421 CLK_TOP_CB_CKSQ_40M>,
422 <&topckgen CLK_TOP_UART_SEL>;
423 status = "disabled";
424 };
425
426 uart1: serial@11000100 {
427 compatible = "mediatek,mt7986-uart",
428 "mediatek,mt6577-uart";
429 reg = <0 0x11000100 0 0x100>;
430 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&infracfg CLK_INFRA_52M_UART1_CK>,
432 <&infracfg CLK_INFRA_66M_UART1_PCK>;
433 clock-names = "baud", "bus";
434 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
435 <&infracfg CLK_INFRA_MUX_UART1_SEL>;
436 assigned-clock-parents = <&topckgen
437 CLK_TOP_CB_CKSQ_40M>,
438 <&topckgen CLK_TOP_UART_SEL>;
439 status = "disabled";
440 };
441
442 uart2: serial@11000200 {
443 compatible = "mediatek,mt7986-uart",
444 "mediatek,mt6577-uart";
445 reg = <0 0x11000200 0 0x100>;
446 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
447 clocks = <&infracfg CLK_INFRA_52M_UART2_CK>,
448 <&infracfg CLK_INFRA_66M_UART2_PCK>;
449 clock-names = "baud", "bus";
450 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
451 <&infracfg CLK_INFRA_MUX_UART2_SEL>;
452 assigned-clock-parents = <&topckgen
453 CLK_TOP_CB_CKSQ_40M>,
454 <&topckgen CLK_TOP_UART_SEL>;
455 status = "disabled";
456 };
457
458 i2c0: i2c@11003000 {
459 compatible = "mediatek,mt7988-i2c",
460 "mediatek,mt7981-i2c";
461 reg = <0 0x11003000 0 0x1000>,
462 <0 0x10217080 0 0x80>;
463 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
464 clock-div = <1>;
465 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
466 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
467 clock-names = "main", "dma";
468 #address-cells = <1>;
469 #size-cells = <0>;
470 status = "disabled";
471 };
472
473 spi0: spi@11007800 {
474 compatible = "mediatek,ipm-spi-quad",
475 "mediatek,spi-ipm";
476 reg = <0 0x11007800 0 0x100>;
477 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
478 clocks = <&topckgen CLK_TOP_CB_M_D2>,
479 <&topckgen CLK_TOP_SPI_SEL>,
480 <&infracfg CLK_INFRA_104M_SPI0>,
481 <&infracfg CLK_INFRA_66M_SPI0_HCK>;
482 assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
483 <&infracfg CLK_INFRA_MUX_SPI0_SEL>;
484 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
485 <&topckgen CLK_TOP_SPI_SEL>;
486 clock-names = "parent-clk", "sel-clk", "spi-clk",
487 "hclk";
488 status = "disabled";
489 };
490
491 spi1: spi@11008800 {
492 compatible = "mediatek,ipm-spi-single",
493 "mediatek,spi-ipm";
494 reg = <0 0x11008800 0 0x100>;
495 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&topckgen CLK_TOP_CB_M_D2>,
497 <&topckgen CLK_TOP_SPI_SEL>,
498 <&infracfg CLK_INFRA_104M_SPI1>,
499 <&infracfg CLK_INFRA_66M_SPI1_HCK>;
500 assigned-clocks = <&topckgen CLK_TOP_SPIM_MST_SEL>,
501 <&infracfg CLK_INFRA_MUX_SPI1_SEL>;
502 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
503 <&topckgen
504 CLK_TOP_SPIM_MST_SEL>;
505 clock-names = "parent-clk", "sel-clk", "spi-clk",
506 "hclk";
507 status = "disabled";
508 };
509
510 spi2: spi@11009800 {
511 compatible = "mediatek,ipm-spi-quad",
512 "mediatek,spi-ipm";
513 reg = <0 0x11009800 0 0x100>;
514 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&topckgen CLK_TOP_CB_M_D2>,
516 <&topckgen CLK_TOP_SPI_SEL>,
517 <&infracfg CLK_INFRA_104M_SPI2_BCK>,
518 <&infracfg CLK_INFRA_66M_SPI2_HCK>;
519 assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
520 <&infracfg
521 CLK_INFRA_MUX_SPI2_BCK_SEL>;
522 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
523 <&topckgen CLK_TOP_SPI_SEL>;
524 clock-names = "parent-clk", "sel-clk", "spi-clk",
525 "hclk";
526 status = "disabled";
527 };
528
529 lvts: lvts@1100a000 {
530 compatible = "mediatek,mt7987-lvts";
531 #thermal-sensor-cells = <1>;
532 reg = <0 0x1100a000 0 0x1000>;
533 clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
534 clock-names = "lvts_clk";
535 nvmem-cells = <&lvts_calibration>;
536 nvmem-cell-names = "e_data1";
537 status = "disabled";
538 };
539
540 usbtphy: usb-phy@11c50000 {
541 compatible = "mediatek,mt7987",
542 "mediatek,generic-tphy-v2";
543 #address-cells = <2>;
544 #size-cells = <2>;
545 ranges;
546
547 tphyu2port0: usb-phy@11c50000 {
548 reg = <0 0x11c50000 0 0x700>;
549 clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
550 clock-names = "ref";
551 #phy-cells = <1>;
552
553 auto_load_valid;
554 nvmem-cells = <&u2_intr_p0>,
555 <&u2_auto_load_valid_p0>;
556 nvmem-cell-names = "intr", "auto_load_valid";
557 };
558
559 tphyu3port0: usb-phy@11c50700 {
560 reg = <0 0x11c50700 0 0x900>;
561 clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
562 clock-names = "ref";
563 #phy-cells = <1>;
564
565 auto_load_valid;
566 nvmem-cells = <&comb_intr_p0>,
567 <&comb_rx_imp_p0>,
568 <&comb_tx_imp_p0>,
569 <&comb_auto_load_valid>;
570 nvmem-cell-names = "intr", "rx_imp", "tx_imp",
571 "auto_load_valid";
572
573 /* MT7987: 4'b0010 default USB30
574 * Don't change the '0'
575 */
576 mediatek,syscon-type = <&topmisc 0x218 0>;
577
578 status = "disabled";
579 };
580 };
581
582 xhci: xhci@11200000 {
583 compatible = "mediatek,mt7987-xhci",
584 "mediatek,mtk-xhci";
585 reg = <0 0x11200000 0 0x2e00>,
586 <0 0x11203e00 0 0x0100>;
587 reg-names = "mac", "ippc";
588 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
589 usb2-lpm-disable;
590 status = "disabled";
591 };
592
593 afe: audio-controller@11210000 {
594 compatible = "mediatek,mt79xx-audio";
595 reg = <0 0x11210000 0 0x9000>;
596 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
597 clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>,
598 <&infracfg CLK_INFRA_AUD_26M>,
599 <&infracfg CLK_INFRA_AUD_L>,
600 <&infracfg CLK_INFRA_AUD_AUD>,
601 <&infracfg CLK_INFRA_AUD_EG2>,
602 <&topckgen CLK_TOP_AUD_SEL>,
603 <&topckgen CLK_TOP_AUD_I2S_M>;
604 clock-names = "aud_bus_ck",
605 "aud_26m_ck",
606 "aud_l_ck",
607 "aud_aud_ck",
608 "aud_eg2_ck",
609 "aud_sel",
610 "aud_i2s_m";
611 assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
612 <&topckgen CLK_TOP_A1SYS_SEL>,
613 <&topckgen CLK_TOP_AUD_L_SEL>,
614 <&topckgen CLK_TOP_A_TUNER_SEL>;
615 assigned-clock-parents = <&apmixedsys
616 CLK_APMIXED_APLL2>,
617 <&topckgen
618 CLK_TOP_CB_APLL2_D4>,
619 <&apmixedsys
620 CLK_APMIXED_APLL2>,
621 <&topckgen
622 CLK_TOP_CB_APLL2_D4>;
623 status = "disabled";
624 };
625
626 mmc0: mmc@11230000 {
627 #address-cells = <1>;
628 #size-cells = <0>;
629 compatible = "mediatek,mt7986-mmc";
630 reg = <0 0x11230000 0 0x1000>,
631 <0 0x11f50000 0 0x1000>;
632 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
633 clocks = <&topckgen CLK_TOP_EMMC_200M_SEL>,
634 <&infracfg CLK_INFRA_MSDC400>,
635 <&infracfg CLK_INFRA_133M_MSDC_0_HCK>,
636 <&infracfg CLK_INFRA_MSDC2_HCK>,
637 <&infracfg CLK_INFRA_MSDC200_SRC>,
638 <&infracfg CLK_INFRA_66M_MSDC_0_HCK>;
639 clock-names = "source", "bus_clk", "axi_cg", "hclk",
640 "source_cg", "ahb_cg";
641 status = "disabled";
642 };
643
644 wed: wed {
645 compatible = "mediatek,wed";
646 wed_num = <1>;
647 };
648
649 wed0: wed0@15010000 {
650 compatible = "mediatek,wed0";
651 /* add this property for wed get the pci slot number */
652 pci_slot_map = <0>;
653 reg = <0 0x15010000 0 0x2000>;
654 interrupt-parent = <&gic>;
655 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
656 };
657
658 wdma: wdma@15104800 {
659 compatible = "mediatek,wed-wdma";
660 reg = <0 0x15104800 0 0x400>;
661 };
662
663 pcie0: pcie@11280000 {
664 compatible = "mediatek,mt7988-pcie",
665 "mediatek,mt7987-pcie",
666 "mediatek,mt7986-pcie";
667 device_type = "pci";
668 #address-cells = <3>;
669 #size-cells = <2>;
670 reg = <0 0x11280000 0 0x2000>;
671 reg-names = "pcie-mac";
672 linux,pci-domain = <0>;
673 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
674 bus-range = <0x00 0xff>;
675 ranges = <0x81000000 0x00 0x20000000 0x00
676 0x20000000 0x00 0x00200000>,
677 <0x82000000 0x00 0x20200000 0x00
678 0x20200000 0x00 0x0fe00000>;
679 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
680 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
681 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
682 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
683 clock-names = "pl_250m", "tl_26m", "peri_26m",
684 "top_133m";
685 status = "disabled";
686 #interrupt-cells = <1>;
687 interrupt-map-mask = <0 0 0 0x7>;
688 interrupt-map = <0 0 0 1 &pcie_intc2 0>,
689 <0 0 0 2 &pcie_intc2 1>,
690 <0 0 0 3 &pcie_intc2 2>,
691 <0 0 0 4 &pcie_intc2 3>;
692 pcie_intc2: interrupt-controller {
693 #address-cells = <0>;
694 #interrupt-cells = <1>;
695 interrupt-controller;
696 };
697 };
698
699 pcie1: pcie@11290000 {
700 compatible = "mediatek,mt7988-pcie",
701 "mediatek,mt7987-pcie",
702 "mediatek,mt7986-pcie";
703 device_type = "pci";
704 #address-cells = <3>;
705 #size-cells = <2>;
706 reg = <0 0x11290000 0 0x2000>;
707 reg-names = "pcie-mac";
708 linux,pci-domain = <1>;
709 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
710 bus-range = <0x00 0xff>;
711 ranges = <0x81000000 0x00 0x30000000 0x00
712 0x30000000 0x00 0x00200000>,
713 <0x82000000 0x00 0x30200000 0x00
714 0x30200000 0x00 0x0fe00000>;
715 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
716 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
717 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
718 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
719 clock-names = "pl_250m", "tl_26m", "peri_26m",
720 "top_133m";
721 status = "disabled";
722 #interrupt-cells = <1>;
723 interrupt-map-mask = <0 0 0 0x7>;
724 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
725 <0 0 0 2 &pcie_intc1 1>,
726 <0 0 0 3 &pcie_intc1 2>,
727 <0 0 0 4 &pcie_intc1 3>;
728 pcie_intc1: interrupt-controller {
729 #address-cells = <0>;
730 #interrupt-cells = <1>;
731 interrupt-controller;
732 };
733 slot1: pcie@0,0 {
734 reg = <0x0000 0 0 0 0>;
735 };
736 };
737
738 topmisc: topmisc@10021000 {
739 compatible = "mediatek,mt7987-topmisc", "syscon",
740 "mediatek,mt7987-power-controller";
741 reg = <0 0x10021000 0 0x10000>;
742 #clock-cells = <1>;
743 #power-domain-cells = <1>;
744 #address-cells = <1>;
745 #size-cells = <0>;
746 /* power domain of the SoC */
747 /* eth2p5@MT7988_POWER_DOMAIN_ETH2P5 {
748 * reg = <MT7988_POWER_DOMAIN_ETH2P5>;
749 * #power-domain-cells = <0>;
750 * };
751 */
752 };
753
754 efuse: efuse@11d30000 {
755 compatible = "mediatek,efuse";
756 reg = <0 0x11d30000 0 0x1000>;
757 #address-cells = <1>;
758 #size-cells = <1>;
759
760 lvts_calibration: calib@918 {
761 reg = <0x918 0x10>;
762 };
763
764 comb_auto_load_valid: usb3-alv-imp@8ee {
765 reg = <0x8ee 1>;
766 bits = <0 1>;
767 };
768
769 comb_rx_imp_p0: usb3-rx-imp@8ec {
770 reg = <0x8ec 1>;
771 bits = <0 5>;
772 };
773
774 comb_tx_imp_p0: usb3-tx-imp@8ec {
775 reg = <0x8ec 2>;
776 bits = <5 5>;
777 };
778
779 comb_intr_p0: usb3-intr@8ec {
780 reg = <0x8ec 2>;
781 bits = <10 6>;
782 };
783
784 u2_auto_load_valid_p0: usb2-alv-p0@8cc {
785 reg = <0x8cc 1>;
786 bits = <0 1>;
787 };
788
789 u2_intr_p0: usb2-intr-p0@8cc {
790 reg = <0x8cc 1>;
791 bits = <1 5>;
792 };
793 };
794
795 devapc: devapc@1a110000 {
796 compatible = "mediatek,mt7987-devapc";
797 reg = <0 0x1a110000 0 0x1000>;
798 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
799 };
800 };
801
802 netsys: soc_netsys {
803 #address-cells = <2>;
804 #size-cells = <2>;
805 compatible = "simple-bus";
806 ranges;
807 };
808};