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developer15dd2c82022-09-09 19:59:16 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 */
6
7/dts-v1/;
8#include "mt7981.dtsi"
9#include <dt-bindings/gpio/gpio.h>
10
11/ {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 model = "mt7981-rfb";
15 compatible = "mediatek,mt7981", "mediatek,mt7981-rfb";
16 chosen {
17 stdout-path = &uart0;
18 tick-timer = &timer0;
19 };
20
developer87bf1bc2023-07-19 17:15:41 +080021 memory@40000000 {
22 device_type = "memory";
23 reg = <0x40000000 0x10000000>;
24 };
25
developer15dd2c82022-09-09 19:59:16 +080026 reg_3p3v: regulator-3p3v {
27 compatible = "regulator-fixed";
28 regulator-name = "fixed-3.3V";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
31 regulator-boot-on;
32 regulator-always-on;
33 };
34};
35
36&uart0 {
37 status = "okay";
38};
39
40&uart1 {
41 pinctrl-names = "default";
42 pinctrl-0 = <&uart1_pins>;
43 status = "disabled";
44};
45
46&eth {
47 status = "okay";
48 mediatek,gmac-id = <0>;
developer31f7ad62023-07-19 17:17:18 +080049 phy-mode = "2500base-x";
developer27686ad2025-02-05 09:24:37 +080050 mediatek,switch = "auto";
Christian Marangi68d05782025-01-27 14:40:43 +010051 reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
developer15dd2c82022-09-09 19:59:16 +080052
53 fixed-link {
developer31f7ad62023-07-19 17:17:18 +080054 speed = <2500>;
developer15dd2c82022-09-09 19:59:16 +080055 full-duplex;
56 };
57};
58
Christian Marangi68d05782025-01-27 14:40:43 +010059&pio {
developer15dd2c82022-09-09 19:59:16 +080060 spic_pins: spi1-pins-func-1 {
61 mux {
62 function = "spi";
63 groups = "spi1_1";
64 };
65 };
66
67 uart1_pins: spi1-pins-func-3 {
68 mux {
69 function = "uart";
70 groups = "uart1_2";
71 };
72 };
73
74 /* pin15 as pwm0 */
75 one_pwm_pins: one-pwm-pins {
76 mux {
77 function = "pwm";
78 groups = "pwm0_1";
79 };
80 };
81
82 /* pin15 as pwm0 and pin14 as pwm1 */
83 two_pwm_pins: two-pwm-pins {
84 mux {
85 function = "pwm";
86 groups = "pwm0_1", "pwm1_0";
87 };
88 };
89
90 /* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */
91 three_pwm_pins: three-pwm-pins {
92 mux {
93 function = "pwm";
94 groups = "pwm0_1", "pwm1_0", "pwm2";
95 };
96 };
97
developerd24fd7e2025-01-17 17:18:06 +080098 /* pin13 as pwm0, pin15 as pwm1, pin7 as pwm2 */
99 three_pwm_pins_1: three-pwm-pins {
100 mux {
101 function = "pwm";
102 groups = "pwm0_0", "pwm1_1", "pwm2";
103 };
104 };
105
developer15dd2c82022-09-09 19:59:16 +0800106 mmc0_pins_default: mmc0default {
107 mux {
108 function = "flash";
109 groups = "emmc_45";
110 };
111 conf-cmd-dat {
112 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
113 "SPI0_CS", "SPI0_HOLD", "SPI0_WP",
114 "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
115 input-enable;
116 drive-strength = <MTK_DRIVE_4mA>;
117 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
118 };
119 conf-clk {
120 pins = "SPI1_CS";
121 drive-strength = <MTK_DRIVE_6mA>;
122 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
123 };
124 conf-rst {
125 pins = "PWM0";
126 drive-strength = <MTK_DRIVE_4mA>;
127 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
128 };
129 };
130};
131
132&pwm {
133 pinctrl-names = "default";
134 pinctrl-0 = <&two_pwm_pins>;
135 status = "okay";
136};
137
138&watchdog {
139 status = "disabled";
140};
141
142&mmc0 {
143 pinctrl-names = "default";
144 pinctrl-0 = <&mmc0_pins_default>;
145 bus-width = <8>;
146 max-frequency = <52000000>;
147 cap-mmc-highspeed;
148 cap-mmc-hw-reset;
149 vmmc-supply = <&reg_3p3v>;
150 non-removable;
151 status = "okay";
152};