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git01.mediatek.com / filogic / uboot / bf7c0cee160adfa8cbea76491b51fb492d1bf9ba / . / arch / arm / dts / k3-am62a7-r5-sk.dts
blob: 49e62533a951ba1509bfe24cf3b68fd9005d9a61 [file] [log] [blame]
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * AM62A7 SK dts file for R5 SPL
4 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
5 */
6
7#include "k3-am62a7-sk.dts"
8#include "k3-am62a-ddr-1866mhz-32bit.dtsi"
9#include "k3-am62a-ddr.dtsi"
10
11#include "k3-am62a7-sk-u-boot.dtsi"
12
13/ {
14 aliases {
Manorit Chawdhry1e081eb2024-11-21 17:32:51 +0530[diff] [blame]15 tick-timer = &main_timer0;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]16 remoteproc0 = &sysctrler;
17 remoteproc1 = &a53_0;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]18 };
19
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]20 a53_0: a53@0 {
21 compatible = "ti,am654-rproc";
22 reg = <0x00 0x00a90000 0x00 0x10>;
23 power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
Manorit Chawdhry5c760a62023-04-14 09:47:58 +0530[diff] [blame]24 <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
25 <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]26 resets = <&k3_reset 135 0>;
Manorit Chawdhryf23728b2024-10-15 16:22:19 +0530[diff] [blame]27 clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
28 clock-names = "gtc", "core";
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]29 assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
30 assigned-clock-parents = <&k3_clks 61 2>;
31 assigned-clock-rates = <200000000>, <1200000000>;
32 ti,sci = <&dmsc>;
33 ti,sci-proc-id = <32>;
34 ti,sci-host-id = <10>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]35 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]36 };
37
38 dm_tifs: dm-tifs {
39 compatible = "ti,j721e-dm-sci";
40 ti,host-id = <36>;
41 ti,secure-host;
42 mbox-names = "rx", "tx";
43 mboxes= <&secure_proxy_main 22>,
44 <&secure_proxy_main 23>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]46 };
47};
48
49&dmsc {
50 mboxes= <&secure_proxy_main 0>,
51 <&secure_proxy_main 1>,
52 <&secure_proxy_main 0>;
53 mbox-names = "rx", "tx", "notify";
54 ti,host-id = <35>;
55 ti,secure-host;
56};
57
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]58&secure_proxy_sa3 {
59 /* Needed for initial handshake with ROM */
60 status = "okay";
61 bootph-pre-ram;
62};
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]63
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]64&cbass_main {
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]65 sysctrler: sysctrler {
66 compatible = "ti,am654-system-controller";
67 mboxes= <&secure_proxy_main 1>,
68 <&secure_proxy_main 0>,
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]69 <&secure_proxy_sa3 0>;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]70 mbox-names = "tx", "rx", "boot_notify";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]71 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]72 };
73};
74
Manorit Chawdhry1e081eb2024-11-21 17:32:51 +0530[diff] [blame]75&main_timer0 {
76 /delete-property/ clocks;
77 /delete-property/ clocks-names;
78 /delete-property/ assigned-clocks;
79 /delete-property/ assigned-clock-parents;
80 clock-frequency = <25000000>;
81 bootph-pre-ram;
82};
83
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]84&wkup_uart0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]85 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]86};
87
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]88&main_uart1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]89 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]90};
91
92/* WKUP UART0 is used for DM firmware logs */
93&wkup_uart0 {
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]94 status = "okay";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]95 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]96};
97
98/* Main UART1 is used for TIFS firmware logs */
99&main_uart1 {
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]100 status = "okay";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]101 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]102};