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git01.mediatek.com / filogic / uboot / bf7c0cee160adfa8cbea76491b51fb492d1bf9ba / . / arch / arm / dts / imx8mp-dhcom-u-boot.dtsi
blob: 546490a4a8187118191b72dd98bdd5bc54526e1a [file] [log] [blame]
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2022 Marek Vasut <marex@denx.de>
4 */
5
6#include "imx8mp-u-boot.dtsi"
7
8/ {
9 aliases {
10 eeprom0 = &eeprom0;
11 eeprom1 = &eeprom1;
Christoph Niedermaier7a469592024-12-07 00:04:17 +0100[diff] [blame]12 eeprom0wl = &eeprom0wl;
13 eeprom1wl = &eeprom1wl;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]14 mmc0 = &usdhc2; /* MicroSD */
15 mmc1 = &usdhc3; /* eMMC */
16 mmc2 = &usdhc1; /* SDIO */
17 };
18
19 config {
20 dh,ram-coding-gpios = <&gpio3 22 0>, <&gpio3 23 0>, <&gpio3 24 0>;
21 };
22
23 wdt-reboot {
24 compatible = "wdt-reboot";
25 wdt = <&wdog1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]26 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]27 };
28};
29
30&buck4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]31 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]32};
33
34&buck5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]35 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]36};
37
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]38&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]39 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]40};
41
42&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]43 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]44};
45
46&gpio3 {
Marek Vasutc916b282023-10-16 00:41:14 +0200[diff] [blame]47 bootph-all;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]48 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]49};
50
51&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]52 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]53};
54
55&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]56 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]57};
58
59&i2c3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]60 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]61};
62
63&pinctrl_i2c3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]64 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]65};
66
67&pinctrl_i2c3_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]68 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]69};
70
71&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]72 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]73};
74
75&pinctrl_uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]76 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]77};
78
79&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]80 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]81};
82
83&pinctrl_usdhc2_100mhz {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]84 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]85};
86
87&pinctrl_usdhc2_200mhz {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]88 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]89};
90
91&pinctrl_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]92 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]93};
94
95&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]96 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]97};
98
99&pinctrl_usdhc3_100mhz {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]100 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]101};
102
103&pinctrl_usdhc3_100mhz {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]104 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]105};
106
107&pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]108 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]109
110 regulators {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]111 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]112 };
113};
114
115&reg_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]116 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]117};
118
119&uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]120 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]121};
122
123/* SDIO WiFi */
124&usdhc1 {
125 status = "disabled";
126};
127
128&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]129 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]130};
131
132&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]133 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]134};
135
136&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]137 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]138};
Marek Vasut5ca41212023-09-21 20:44:17 +0200[diff] [blame]139
Marek Vasut9fe526d2024-05-21 12:48:24 +0200[diff] [blame]140&binman_imx_fit {
141 images {
142 fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast {
143 description = "imx8mp-dhcom-som-overlay-eth1xfast";
144 type = "flat_dt";
145 compression = "none";
Marek Vasut5ca41212023-09-21 20:44:17 +0200[diff] [blame]146
Marek Vasut9fe526d2024-05-21 12:48:24 +0200[diff] [blame]147 blob-ext {
148 filename = "imx8mp-dhcom-som-overlay-eth1xfast.dtbo";
149 };
150 };
Marek Vasut5ca41212023-09-21 20:44:17 +0200[diff] [blame]151
Marek Vasut9fe526d2024-05-21 12:48:24 +0200[diff] [blame]152 fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast {
153 description = "imx8mp-dhcom-som-overlay-eth2xfast";
154 type = "flat_dt";
155 compression = "none";
Marek Vasut5ca41212023-09-21 20:44:17 +0200[diff] [blame]156
Marek Vasut9fe526d2024-05-21 12:48:24 +0200[diff] [blame]157 blob-ext {
158 filename = "imx8mp-dhcom-som-overlay-eth2xfast.dtbo";
159 };
160 };
Marek Vasut5ca41212023-09-21 20:44:17 +0200[diff] [blame]161
Marek Vasut9fe526d2024-05-21 12:48:24 +0200[diff] [blame]162 fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast {
163 description = "imx8mp-dhcom-pdk-overlay-eth2xfast";
164 type = "flat_dt";
165 compression = "none";
Marek Vasut5ca41212023-09-21 20:44:17 +0200[diff] [blame]166
Marek Vasut9fe526d2024-05-21 12:48:24 +0200[diff] [blame]167 blob-ext {
168 filename = "imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo";
169 };
170 };
Marek Vasut792cb562023-09-21 20:44:18 +0200[diff] [blame]171
Marek Vasut9fe526d2024-05-21 12:48:24 +0200[diff] [blame]172 fdt-dto-imx8mp-dhcom-som-overlay-rev100 {
173 description = "imx8mp-dhcom-som-overlay-rev100";
174 type = "flat_dt";
175 compression = "none";
Marek Vasut792cb562023-09-21 20:44:18 +0200[diff] [blame]176
Marek Vasut9fe526d2024-05-21 12:48:24 +0200[diff] [blame]177 blob-ext {
178 filename = "imx8mp-dhcom-som-overlay-rev100.dtbo";
179 };
180 };
Marek Vasut792cb562023-09-21 20:44:18 +0200[diff] [blame]181
Marek Vasut9fe526d2024-05-21 12:48:24 +0200[diff] [blame]182 fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100 {
183 description = "imx8mp-dhcom-pdk3-overlay-rev100";
184 type = "flat_dt";
185 compression = "none";
Marek Vasut792cb562023-09-21 20:44:18 +0200[diff] [blame]186
Marek Vasut9fe526d2024-05-21 12:48:24 +0200[diff] [blame]187 blob-ext {
188 filename = "imx8mp-dhcom-pdk3-overlay-rev100.dtbo";
Marek Vasut5ca41212023-09-21 20:44:17 +0200[diff] [blame]189 };
Marek Vasut9fe526d2024-05-21 12:48:24 +0200[diff] [blame]190 };
191 };
Marek Vasut5ca41212023-09-21 20:44:17 +0200[diff] [blame]192
Marek Vasut9fe526d2024-05-21 12:48:24 +0200[diff] [blame]193 configurations {
194 default = "@config-DEFAULT-SEQ";
Marek Vasut5ca41212023-09-21 20:44:17 +0200[diff] [blame]195
Marek Vasut9fe526d2024-05-21 12:48:24 +0200[diff] [blame]196 @config-SEQ {
197 fdt = "fdt-1",
198 "fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast",
199 "fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast",
200 "fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast",
201 "fdt-dto-imx8mp-dhcom-som-overlay-rev100",
202 "fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100";
Marek Vasut5ca41212023-09-21 20:44:17 +0200[diff] [blame]203 };
204 };
205};