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git01.mediatek.com / filogic / uboot / bf7c0cee160adfa8cbea76491b51fb492d1bf9ba / . / arch / arm / dts / at91sam9n12.dtsi
blob: 84089837013de280f08650e67c3e9564e1e1b2f6 [file] [log] [blame]
Wenyou Yangdf08ad72017-04-18 13:49:35 +0800[diff] [blame]1/*
2 * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Hong Xu <hong.xu@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10#include "skeleton.dtsi"
11#include <dt-bindings/dma/at91.h>
12#include <dt-bindings/pinctrl/at91.h>
13#include <dt-bindings/interrupt-controller/irq.h>
14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/clock/at91.h>
16
17/ {
18 model = "Atmel AT91SAM9N12 SoC";
19 compatible = "atmel,at91sam9n12";
20 interrupt-parent = <&aic>;
21
22 aliases {
23 serial0 = &dbgu;
24 serial1 = &usart0;
25 serial2 = &usart1;
26 serial3 = &usart2;
27 serial4 = &usart3;
28 gpio0 = &pioA;
29 gpio1 = &pioB;
30 gpio2 = &pioC;
31 gpio3 = &pioD;
32 tcb0 = &tcb0;
33 tcb1 = &tcb1;
34 i2c0 = &i2c0;
35 i2c1 = &i2c1;
36 ssc0 = &ssc0;
37 pwm0 = &pwm0;
38 spi0 = &spi0;
39 };
40 cpus {
Wenyou Yangdf08ad72017-04-18 13:49:35 +0800[diff] [blame]41 cpu {
42 compatible = "arm,arm926ej-s";
43 device_type = "cpu";
44 };
45 };
46
47 memory {
48 reg = <0x20000000 0x10000000>;
49 };
50
51 clocks {
52 slow_xtal: slow_xtal {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <0>;
56 };
57
58 main_xtal: main_xtal {
59 compatible = "fixed-clock";
60 #clock-cells = <0>;
61 clock-frequency = <0>;
62 };
63 };
64
65 sram: sram@00300000 {
66 compatible = "mmio-sram";
67 reg = <0x00300000 0x8000>;
68 };
69
70 ahb {
71 compatible = "simple-bus";
72 #address-cells = <1>;
73 #size-cells = <1>;
74 ranges;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]75 bootph-all;
Wenyou Yangdf08ad72017-04-18 13:49:35 +0800[diff] [blame]76
77 apb {
78 compatible = "simple-bus";
79 #address-cells = <1>;
80 #size-cells = <1>;
81 ranges;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]82 bootph-all;
Wenyou Yangdf08ad72017-04-18 13:49:35 +0800[diff] [blame]83
84 aic: interrupt-controller@fffff000 {
85 #interrupt-cells = <3>;
86 compatible = "atmel,at91rm9200-aic";
87 interrupt-controller;
88 reg = <0xfffff000 0x200>;
89 atmel,external-irqs = <31>;
90 };
91
92 ramc0: ramc@ffffe800 {
93 compatible = "atmel,at91sam9g45-ddramc";
94 reg = <0xffffe800 0x200>;
95 clocks = <&ddrck>;
96 clock-names = "ddrck";
97 };
98
99 pmc: pmc@fffffc00 {
100 compatible = "atmel,at91sam9n12-pmc", "syscon";
101 reg = <0xfffffc00 0x200>;
102 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
103 interrupt-controller;
104 #address-cells = <1>;
105 #size-cells = <0>;
106 #interrupt-cells = <1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]107 bootph-all;
Wenyou Yangdf08ad72017-04-18 13:49:35 +0800[diff] [blame]108
109 main_rc_osc: main_rc_osc {
110 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
111 #clock-cells = <0>;
112 interrupts-extended = <&pmc AT91_PMC_MOSCRCS>;
113 clock-frequency = <12000000>;
114 clock-accuracy = <50000000>;
115 };
116
117 main_osc: main_osc {
118 compatible = "atmel,at91rm9200-clk-main-osc";
119 #clock-cells = <0>;
120 interrupts-extended = <&pmc AT91_PMC_MOSCS>;
121 clocks = <&main_xtal>;
122 };
123
124 main: mainck {
125 compatible = "atmel,at91sam9x5-clk-main";
126 #clock-cells = <0>;
127 interrupts-extended = <&pmc AT91_PMC_MOSCSELS>;
128 clocks = <&main_rc_osc>, <&main_osc>;
129 };
130
131 plla: pllack@0 {
132 compatible = "atmel,at91rm9200-clk-pll";
133 #clock-cells = <0>;
134 interrupts-extended = <&pmc AT91_PMC_LOCKA>;
135 clocks = <&main>;
136 reg = <0>;
137 atmel,clk-input-range = <2000000 32000000>;
138 #atmel,pll-clk-output-range-cells = <4>;
139 atmel,pll-clk-output-ranges = <745000000 800000000 0 0>,
140 <695000000 750000000 1 0>,
141 <645000000 700000000 2 0>,
142 <595000000 650000000 3 0>,
143 <545000000 600000000 0 1>,
144 <495000000 555000000 1 1>,
145 <445000000 500000000 2 1>,
146 <400000000 450000000 3 1>;
147 };
148
149 plladiv: plladivck {
150 compatible = "atmel,at91sam9x5-clk-plldiv";
151 #clock-cells = <0>;
152 clocks = <&plla>;
153 };
154
155 pllb: pllbck@1 {
156 compatible = "atmel,at91rm9200-clk-pll";
157 #clock-cells = <0>;
158 interrupts-extended = <&pmc AT91_PMC_LOCKB>;
159 clocks = <&main>;
160 reg = <1>;
161 atmel,clk-input-range = <2000000 32000000>;
162 #atmel,pll-clk-output-range-cells = <3>;
163 atmel,pll-clk-output-ranges = <30000000 100000000 0>;
164 };
165
166 mck: masterck {
167 compatible = "atmel,at91sam9x5-clk-master";
168 #clock-cells = <0>;
169 interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
170 clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>;
171 atmel,clk-output-range = <0 133333333>;
172 atmel,clk-divisors = <1 2 4 3>;
173 atmel,master-clk-have-div3-pres;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]174 bootph-all;
Wenyou Yangdf08ad72017-04-18 13:49:35 +0800[diff] [blame]175 };
176
177 usb: usbck {
178 compatible = "atmel,at91sam9n12-clk-usb";
179 #clock-cells = <0>;
180 clocks = <&pllb>;
181 };
182
183 prog: progck {
184 compatible = "atmel,at91sam9x5-clk-programmable";
185 #address-cells = <1>;
186 #size-cells = <0>;
187 interrupt-parent = <&pmc>;
188 clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>, <&mck>;
189
190 prog0: prog@0 {
191 #clock-cells = <0>;
192 reg = <0>;
193 interrupts = <AT91_PMC_PCKRDY(0)>;
194 };
195
196 prog1: prog@1 {
197 #clock-cells = <0>;
198 reg = <1>;
199 interrupts = <AT91_PMC_PCKRDY(1)>;
200 };
201 };
202
203 systemck {
204 compatible = "atmel,at91rm9200-clk-system";
205 #address-cells = <1>;
206 #size-cells = <0>;
207
208 ddrck: ddrck@2 {
209 #clock-cells = <0>;
210 reg = <2>;
211 clocks = <&mck>;
212 };
213
214 lcdck: lcdck@3 {
215 #clock-cells = <0>;
216 reg = <3>;
217 clocks = <&mck>;
218 };
219
220 uhpck: uhpck@6 {
221 #clock-cells = <0>;
222 reg = <6>;
223 clocks = <&usb>;
224 };
225
226 udpck: udpck@7 {
227 #clock-cells = <0>;
228 reg = <7>;
229 clocks = <&usb>;
230 };
231
232 pck0: pck0@8 {
233 #clock-cells = <0>;
234 reg = <8>;
235 clocks = <&prog0>;
236 };
237
238 pck1: pck1@9 {
239 #clock-cells = <0>;
240 reg = <9>;
241 clocks = <&prog1>;
242 };
243 };
244
245 periphck {
246 compatible = "atmel,at91sam9x5-clk-peripheral";
247 #address-cells = <1>;
248 #size-cells = <0>;
249 clocks = <&mck>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]250 bootph-all;
Wenyou Yangdf08ad72017-04-18 13:49:35 +0800[diff] [blame]251
252 pioAB_clk: pioAB_clk@2 {
253 #clock-cells = <0>;
254 reg = <2>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]255 bootph-all;
Wenyou Yangdf08ad72017-04-18 13:49:35 +0800[diff] [blame]256 };
257
258 pioCD_clk: pioCD_clk@3 {
259 #clock-cells = <0>;
260 reg = <3>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]261 bootph-all;
Wenyou Yangdf08ad72017-04-18 13:49:35 +0800[diff] [blame]262 };
263
264 fuse_clk: fuse_clk@4 {
265 #clock-cells = <0>;
266 reg = <4>;
267 };
268
269 usart0_clk: usart0_clk@5 {
270 #clock-cells = <0>;
271 reg = <5>;
272 };
273
274 usart1_clk: usart1_clk@6 {
275 #clock-cells = <0>;
276 reg = <6>;
277 };
278
279 usart2_clk: usart2_clk@7 {
280 #clock-cells = <0>;
281 reg = <7>;
282 };
283
284 usart3_clk: usart3_clk@8 {
285 #clock-cells = <0>;
286 reg = <8>;
287 };
288
289 twi0_clk: twi0_clk@9 {
290 reg = <9>;
291 #clock-cells = <0>;
292 };
293
294 twi1_clk: twi1_clk@10 {
295 #clock-cells = <0>;
296 reg = <10>;
297 };
298
299 mci0_clk: mci0_clk@12 {
300 #clock-cells = <0>;
301 reg = <12>;
302 };
303
304 spi0_clk: spi0_clk@13 {
305 #clock-cells = <0>;
306 reg = <13>;
307 };
308
309 spi1_clk: spi1_clk@14 {
310 #clock-cells = <0>;
311 reg = <14>;
312 };
313
314 uart0_clk: uart0_clk@15 {
315 #clock-cells = <0>;
316 reg = <15>;
317 };
318
319 uart1_clk: uart1_clk@16 {
320 #clock-cells = <0>;
321 reg = <16>;
322 };
323
324 tcb_clk: tcb_clk@17 {
325 #clock-cells = <0>;
326 reg = <17>;
327 };
328
329 pwm_clk: pwm_clk@18 {
330 #clock-cells = <0>;
331 reg = <18>;
332 };
333
334 adc_clk: adc_clk@19 {
335 #clock-cells = <0>;
336 reg = <19>;
337 };
338
339 dma0_clk: dma0_clk@20 {
340 #clock-cells = <0>;
341 reg = <20>;
342 };
343
344 uhphs_clk: uhphs_clk@22 {
345 #clock-cells = <0>;
346 reg = <22>;
347 };
348
349 udphs_clk: udphs_clk@23 {
350 #clock-cells = <0>;
351 reg = <23>;
352 };
353
354 lcdc_clk: lcdc_clk@25 {
355 #clock-cells = <0>;
356 reg = <25>;
357 };
358
359 sha_clk: sha_clk@27 {
360 #clock-cells = <0>;
361 reg = <27>;
362 };
363
364 ssc0_clk: ssc0_clk@28 {
365 #clock-cells = <0>;
366 reg = <28>;
367 };
368
369 aes_clk: aes_clk@29 {
370 #clock-cells = <0>;
371 reg = <29>;
372 };
373
374 trng_clk: trng_clk@30 {
375 #clock-cells = <0>;
376 reg = <30>;
377 };
378 };
379 };
380
381 rstc@fffffe00 {
382 compatible = "atmel,at91sam9g45-rstc";
383 reg = <0xfffffe00 0x10>;
384 clocks = <&clk32k>;
385 };
386
387 pit: timer@fffffe30 {
388 compatible = "atmel,at91sam9260-pit";
389 reg = <0xfffffe30 0xf>;
390 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
391 clocks = <&mck>;
392 };
393
394 shdwc@fffffe10 {
395 compatible = "atmel,at91sam9x5-shdwc";
396 reg = <0xfffffe10 0x10>;
397 clocks = <&clk32k>;
398 };
399
400 sckc@fffffe50 {
401 compatible = "atmel,at91sam9x5-sckc";
402 reg = <0xfffffe50 0x4>;
403
404 slow_osc: slow_osc {
405 compatible = "atmel,at91sam9x5-clk-slow-osc";
406 #clock-cells = <0>;
407 clocks = <&slow_xtal>;
408 };
409
410 slow_rc_osc: slow_rc_osc {
411 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
412 #clock-cells = <0>;
413 clock-frequency = <32768>;
414 clock-accuracy = <50000000>;
415 };
416
417 clk32k: slck {
418 compatible = "atmel,at91sam9x5-clk-slow";
419 #clock-cells = <0>;
420 clocks = <&slow_rc_osc>, <&slow_osc>;
421 };
422 };
423
424 mmc0: mmc@f0008000 {
425 compatible = "atmel,hsmci";
426 reg = <0xf0008000 0x600>;
427 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
428 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
429 dma-names = "rxtx";
430 clocks = <&mci0_clk>;
431 clock-names = "mci_clk";
432 #address-cells = <1>;
433 #size-cells = <0>;
434 status = "disabled";
435 };
436
437 tcb0: timer@f8008000 {
438 compatible = "atmel,at91sam9x5-tcb";
439 reg = <0xf8008000 0x100>;
440 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
441 clocks = <&tcb_clk>, <&clk32k>;
442 clock-names = "t0_clk", "slow_clk";
443 };
444
445 tcb1: timer@f800c000 {
446 compatible = "atmel,at91sam9x5-tcb";
447 reg = <0xf800c000 0x100>;
448 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
449 clocks = <&tcb_clk>, <&clk32k>;
450 clock-names = "t0_clk", "slow_clk";
451 };
452
453 hlcdc: hlcdc@f8038000 {
454 compatible = "atmel,at91sam9n12-hlcdc";
455 reg = <0xf8038000 0x2000>;
456 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
457 clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
458 clock-names = "periph_clk", "sys_clk", "slow_clk";
459 status = "disabled";
460
461 hlcdc-display-controller {
462 compatible = "atmel,hlcdc-display-controller";
463 #address-cells = <1>;
464 #size-cells = <0>;
465
466 port@0 {
467 #address-cells = <1>;
468 #size-cells = <0>;
469 reg = <0>;
470 };
471 };
472
473 hlcdc_pwm: hlcdc-pwm {
474 compatible = "atmel,hlcdc-pwm";
475 pinctrl-names = "default";
476 pinctrl-0 = <&pinctrl_lcd_pwm>;
477 #pwm-cells = <3>;
478 };
479 };
480
481 dma: dma-controller@ffffec00 {
482 compatible = "atmel,at91sam9g45-dma";
483 reg = <0xffffec00 0x200>;
484 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
485 #dma-cells = <2>;
486 clocks = <&dma0_clk>;
487 clock-names = "dma_clk";
488 };
489
490 pinctrl@fffff400 {
491 #address-cells = <1>;
492 #size-cells = <1>;
493 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
494 ranges = <0xfffff400 0xfffff400 0x800>;
Wenyou Yangdf08ad72017-04-18 13:49:35 +0800[diff] [blame]495
496 atmel,mux-mask = <
497 /* A B C */
498 0xffffffff 0xffe07983 0x00000000 /* pioA */
499 0x00040000 0x00047e0f 0x00000000 /* pioB */
500 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
501 0x003fffff 0x003f8000 0x00000000 /* pioD */
502 >;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]503 bootph-all;
Wenyou Yangdf08ad72017-04-18 13:49:35 +0800[diff] [blame]504
505 /* shared pinctrl settings */
506 dbgu {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]507 bootph-all;
Wenyou Yangdf08ad72017-04-18 13:49:35 +0800[diff] [blame]508 pinctrl_dbgu: dbgu-0 {
509 atmel,pins =
510 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
511 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
512 };
513 };
514
515 lcd {
516 pinctrl_lcd_base: lcd-base-0 {
517 atmel,pins =
518 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */
519 AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */
520 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDISP */
521 AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */
522 AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
523 };
524
525 pinctrl_lcd_pwm: lcd-pwm-0 {
526 atmel,pins = <AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */
527 };
528
529 pinctrl_lcd_rgb888: lcd-rgb-3 {
530 atmel,pins =
531 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
532 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
533 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
534 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
535 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
536 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
537 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
538 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
539 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
540 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
541 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
542 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
543 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
544 AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
545 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
546 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
547 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
548 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
549 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
550 AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
551 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
552 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
553 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
554 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
555 };
556 };
557
558 usart0 {
559 pinctrl_usart0: usart0-0 {
560 atmel,pins =
561 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
562 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA0 periph A */
563 };
564
565 pinctrl_usart0_rts: usart0_rts-0 {
566 atmel,pins =
567 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */
568 };
569
570 pinctrl_usart0_cts: usart0_cts-0 {
571 atmel,pins =
572 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */
573 };
574 };
575
576 usart1 {
577 pinctrl_usart1: usart1-0 {
578 atmel,pins =
579 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
580 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */
581 };
582 };
583
584 usart2 {
585 pinctrl_usart2: usart2-0 {
586 atmel,pins =
587 <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
588 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA7 periph A */
589 };
590
591 pinctrl_usart2_rts: usart2_rts-0 {
592 atmel,pins =
593 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
594 };
595
596 pinctrl_usart2_cts: usart2_cts-0 {
597 atmel,pins =
598 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
599 };
600 };
601
602 usart3 {
603 pinctrl_usart3: usart3-0 {
604 atmel,pins =
605 <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC23 periph B with pullup */
606 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC22 periph B */
607 };
608
609 pinctrl_usart3_rts: usart3_rts-0 {
610 atmel,pins =
611 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
612 };
613
614 pinctrl_usart3_cts: usart3_cts-0 {
615 atmel,pins =
616 <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
617 };
618 };
619
620 uart0 {
621 pinctrl_uart0: uart0-0 {
622 atmel,pins =
623 <AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC9 periph C with pullup */
624 AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC8 periph C */
625 };
626 };
627
628 uart1 {
629 pinctrl_uart1: uart1-0 {
630 atmel,pins =
631 <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC17 periph C with pullup */
632 AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC16 periph C */
633 };
634 };
635
636 nand {
637 pinctrl_nand: nand-0 {
638 atmel,pins =
639 <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY pin pull_up*/
640 AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD4 gpio enable pin pull_up */
641 };
642 };
643
644 mmc0 {
645 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
646 atmel,pins =
647 <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
648 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
649 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */
650 };
651
652 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
653 atmel,pins =
654 <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
655 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
656 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
657 };
658
659 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
660 atmel,pins =
661 <AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */
662 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */
663 AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA13 periph B with pullup */
664 AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA14 periph B with pullup */
665 };
666 };
667
668 ssc0 {
669 pinctrl_ssc0_tx: ssc0_tx-0 {
670 atmel,pins =
671 <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
672 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
673 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */
674 };
675
676 pinctrl_ssc0_rx: ssc0_rx-0 {
677 atmel,pins =
678 <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
679 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
680 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
681 };
682 };
683
684 spi0 {
685 pinctrl_spi0: spi0-0 {
686 atmel,pins =
687 <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */
688 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */
689 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */
690 };
691 };
692
693 spi1 {
694 pinctrl_spi1: spi1-0 {
695 atmel,pins =
696 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */
697 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */
698 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */
699 };
700 };
701
702 i2c0 {
703 pinctrl_i2c0: i2c0-0 {
704 atmel,pins =
705 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
706 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
707 };
708 };
709
710 i2c1 {
711 pinctrl_i2c1: i2c1-0 {
712 atmel,pins =
713 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE
714 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>;
715 };
716 };
717
718 tcb0 {
719 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
720 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
721 };
722
723 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
724 atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
725 };
726
727 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
728 atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
729 };
730
731 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
732 atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
733 };
734
735 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
736 atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
737 };
738
739 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
740 atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
741 };
742
743 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
744 atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
745 };
746
747 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
748 atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
749 };
750
751 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
752 atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
753 };
754 };
755
756 tcb1 {
757 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
758 atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
759 };
760
761 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
762 atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
763 };
764
765 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
766 atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
767 };
768
769 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
770 atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
771 };
772
773 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
774 atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
775 };
776
777 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
778 atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
779 };
780
781 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
782 atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
783 };
784
785 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
786 atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
787 };
788
789 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
790 atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
791 };
792 };
Wenyou Yangdf08ad72017-04-18 13:49:35 +0800[diff] [blame]793
Manikandan Muralidharan7cff76b2025-02-10 12:21:43 +0530[diff] [blame]794 pioA: gpio@fffff400 {
795 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
796 reg = <0xfffff400 0x200>;
797 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
798 #gpio-cells = <2>;
799 gpio-controller;
800 interrupt-controller;
801 #interrupt-cells = <2>;
802 clocks = <&pioAB_clk>;
803 bootph-all;
804 };
Wenyou Yangdf08ad72017-04-18 13:49:35 +0800[diff] [blame]805
Manikandan Muralidharan7cff76b2025-02-10 12:21:43 +0530[diff] [blame]806 pioB: gpio@fffff600 {
807 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
808 reg = <0xfffff600 0x200>;
809 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
810 #gpio-cells = <2>;
811 gpio-controller;
812 interrupt-controller;
813 #interrupt-cells = <2>;
814 clocks = <&pioAB_clk>;
815 bootph-all;
816 };
Wenyou Yangdf08ad72017-04-18 13:49:35 +0800[diff] [blame]817
Manikandan Muralidharan7cff76b2025-02-10 12:21:43 +0530[diff] [blame]818 pioC: gpio@fffff800 {
819 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
820 reg = <0xfffff800 0x200>;
821 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
822 #gpio-cells = <2>;
823 gpio-controller;
824 interrupt-controller;
825 #interrupt-cells = <2>;
826 clocks = <&pioCD_clk>;
827 bootph-all;
828 };
Wenyou Yangdf08ad72017-04-18 13:49:35 +0800[diff] [blame]829
Manikandan Muralidharan7cff76b2025-02-10 12:21:43 +0530[diff] [blame]830 pioD: gpio@fffffa00 {
831 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
832 reg = <0xfffffa00 0x200>;
833 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
834 #gpio-cells = <2>;
835 gpio-controller;
836 interrupt-controller;
837 #interrupt-cells = <2>;
838 clocks = <&pioCD_clk>;
839 bootph-all;
840 };
Wenyou Yangdf08ad72017-04-18 13:49:35 +0800[diff] [blame]841 };
842
843 dbgu: serial@fffff200 {
844 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
845 reg = <0xfffff200 0x200>;
846 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
847 pinctrl-names = "default";
848 pinctrl-0 = <&pinctrl_dbgu>;
849 clocks = <&mck>;
850 clock-names = "usart";
851 status = "disabled";
852 };
853
854 ssc0: ssc@f0010000 {
855 compatible = "atmel,at91sam9g45-ssc";
856 reg = <0xf0010000 0x4000>;
857 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
858 dmas = <&dma 0 AT91_DMA_CFG_PER_ID(21)>,
859 <&dma 0 AT91_DMA_CFG_PER_ID(22)>;
860 dma-names = "tx", "rx";
861 pinctrl-names = "default";
862 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
863 clocks = <&ssc0_clk>;
864 clock-names = "pclk";
865 status = "disabled";
866 };
867
868 usart0: serial@f801c000 {
869 compatible = "atmel,at91sam9260-usart";
870 reg = <0xf801c000 0x4000>;
871 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
872 pinctrl-names = "default";
873 pinctrl-0 = <&pinctrl_usart0>;
874 clocks = <&usart0_clk>;
875 clock-names = "usart";
876 status = "disabled";
877 };
878
879 usart1: serial@f8020000 {
880 compatible = "atmel,at91sam9260-usart";
881 reg = <0xf8020000 0x4000>;
882 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
883 pinctrl-names = "default";
884 pinctrl-0 = <&pinctrl_usart1>;
885 clocks = <&usart1_clk>;
886 clock-names = "usart";
887 status = "disabled";
888 };
889
890 usart2: serial@f8024000 {
891 compatible = "atmel,at91sam9260-usart";
892 reg = <0xf8024000 0x4000>;
893 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
894 pinctrl-names = "default";
895 pinctrl-0 = <&pinctrl_usart2>;
896 clocks = <&usart2_clk>;
897 clock-names = "usart";
898 status = "disabled";
899 };
900
901 usart3: serial@f8028000 {
902 compatible = "atmel,at91sam9260-usart";
903 reg = <0xf8028000 0x4000>;
904 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
905 pinctrl-names = "default";
906 pinctrl-0 = <&pinctrl_usart3>;
907 clocks = <&usart3_clk>;
908 clock-names = "usart";
909 status = "disabled";
910 };
911
912 i2c0: i2c@f8010000 {
913 compatible = "atmel,at91sam9x5-i2c";
914 reg = <0xf8010000 0x100>;
915 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
916 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>,
917 <&dma 1 AT91_DMA_CFG_PER_ID(14)>;
918 dma-names = "tx", "rx";
919 #address-cells = <1>;
920 #size-cells = <0>;
921 pinctrl-names = "default";
922 pinctrl-0 = <&pinctrl_i2c0>;
923 clocks = <&twi0_clk>;
924 status = "disabled";
925 };
926
927 i2c1: i2c@f8014000 {
928 compatible = "atmel,at91sam9x5-i2c";
929 reg = <0xf8014000 0x100>;
930 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
931 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(15)>,
932 <&dma 1 AT91_DMA_CFG_PER_ID(16)>;
933 dma-names = "tx", "rx";
934 #address-cells = <1>;
935 #size-cells = <0>;
936 pinctrl-names = "default";
937 pinctrl-0 = <&pinctrl_i2c1>;
938 clocks = <&twi1_clk>;
939 status = "disabled";
940 };
941
942 spi0: spi@f0000000 {
943 #address-cells = <1>;
944 #size-cells = <0>;
945 compatible = "atmel,at91rm9200-spi";
946 reg = <0xf0000000 0x100>;
947 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
948 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(1)>,
949 <&dma 1 AT91_DMA_CFG_PER_ID(2)>;
950 dma-names = "tx", "rx";
951 pinctrl-names = "default";
952 pinctrl-0 = <&pinctrl_spi0>;
953 clocks = <&spi0_clk>;
954 clock-names = "spi_clk";
955 status = "disabled";
956 };
957
958 spi1: spi@f0004000 {
959 #address-cells = <1>;
960 #size-cells = <0>;
961 compatible = "atmel,at91rm9200-spi";
962 reg = <0xf0004000 0x100>;
963 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
964 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(3)>,
965 <&dma 1 AT91_DMA_CFG_PER_ID(4)>;
966 dma-names = "tx", "rx";
967 pinctrl-names = "default";
968 pinctrl-0 = <&pinctrl_spi1>;
969 clocks = <&spi1_clk>;
970 clock-names = "spi_clk";
971 status = "disabled";
972 };
973
974 watchdog@fffffe40 {
975 compatible = "atmel,at91sam9260-wdt";
976 reg = <0xfffffe40 0x10>;
977 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
978 clocks = <&clk32k>;
979 atmel,watchdog-type = "hardware";
980 atmel,reset-type = "all";
981 atmel,dbg-halt;
982 status = "disabled";
983 };
984
985 rtc@fffffeb0 {
986 compatible = "atmel,at91rm9200-rtc";
987 reg = <0xfffffeb0 0x40>;
988 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
989 clocks = <&clk32k>;
990 status = "disabled";
991 };
992
993 pwm0: pwm@f8034000 {
994 compatible = "atmel,at91sam9rl-pwm";
995 reg = <0xf8034000 0x300>;
996 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
997 #pwm-cells = <3>;
998 clocks = <&pwm_clk>;
999 status = "disabled";
1000 };
1001
1002 usb1: gadget@f803c000 {
1003 compatible = "atmel,at91sam9260-udc";
1004 reg = <0xf803c000 0x4000>;
1005 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
1006 clocks = <&udphs_clk>, <&udpck>;
1007 clock-names = "pclk", "hclk";
1008 status = "disabled";
1009 };
1010 };
1011
1012 nand0: nand@40000000 {
1013 compatible = "atmel,at91rm9200-nand";
1014 #address-cells = <1>;
1015 #size-cells = <1>;
1016 reg = < 0x40000000 0x10000000
1017 0xffffe000 0x00000600
1018 0xffffe600 0x00000200
1019 0x00108000 0x00018000
1020 >;
1021 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
1022 atmel,nand-addr-offset = <21>;
1023 atmel,nand-cmd-offset = <22>;
1024 atmel,nand-has-dma;
1025 pinctrl-names = "default";
1026 pinctrl-0 = <&pinctrl_nand>;
1027 gpios = <&pioD 5 GPIO_ACTIVE_HIGH
1028 &pioD 4 GPIO_ACTIVE_HIGH
1029 0
1030 >;
1031 status = "disabled";
1032 };
1033
1034 usb0: ohci@00500000 {
1035 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1036 reg = <0x00500000 0x00100000>;
1037 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1038 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
1039 clock-names = "ohci_clk", "hclk", "uhpck";
1040 status = "disabled";
1041 };
1042 };
1043
1044 i2c-gpio-0 {
1045 compatible = "i2c-gpio";
1046 gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
1047 &pioA 31 GPIO_ACTIVE_HIGH /* scl */
1048 >;
1049 i2c-gpio,sda-open-drain;
1050 i2c-gpio,scl-open-drain;
1051 i2c-gpio,delay-us = <2>; /* ~100 kHz */
1052 #address-cells = <1>;
1053 #size-cells = <0>;
1054 status = "disabled";
1055 };
1056};