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git01.mediatek.com / filogic / uboot / bf6e041c51e4dee1bc7706a3a9ecc559ba67dbbc / . / arch / arm / dts / k3-j721e-r5-sk.dts
blob: 96a13b2cb2b93336fa3d2e6e365cc7ce07433e6f [file] [log] [blame]
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
Neha Malcom Francisbe557e92023-09-27 18:39:55 +0530[diff] [blame]8#include "k3-j721e-sk.dts"
Sinthu Rajabb23e8e2021-11-02 19:59:45 +0530[diff] [blame]9#include "k3-j721e-ddr-sk-lp4-4266.dtsi"
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]10#include "k3-j721e-ddr.dtsi"
Neha Malcom Francisbe557e92023-09-27 18:39:55 +0530[diff] [blame]11#include "k3-j721e-sk-u-boot.dtsi"
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]12
Neha Malcom Francis41046502024-05-20 15:29:14 +0530[diff] [blame]13#include "k3-j721e-r5.dtsi"
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]14
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]15&mcu_uart0_pins_default {
16 bootph-pre-ram;
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]17};
18
19&wkup_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]20 bootph-pre-ram;
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]21 tps659412: tps659412@48 {
22 reg = <0x48>;
23 compatible = "ti,tps659412";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]24 bootph-pre-ram;
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]25 pinctrl-names = "default";
26 pinctrl-0 = <&wkup_i2c0_pins_default>;
27 clock-frequency = <400000>;
28
29 regulators: regulators {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]30 bootph-pre-ram;
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]31 /* 3 Phase Buck */
32 buck123_reg: buck123 {
33 /* VDD_CPU */
34 regulator-name = "buck123";
35 regulator-min-microvolt = <800000>;
36 regulator-max-microvolt = <1250000>;
37 regulator-always-on;
38 regulator-boot-on;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]39 bootph-pre-ram;
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]40 };
41 };
Neha Malcom Francisbe557e92023-09-27 18:39:55 +0530[diff] [blame]42
43 esm: esm {
44 compatible = "ti,tps659413-esm";
45 bootph-pre-ram;
46 };
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]47 };
48};
49
50&wkup_vtm0 {
51 vdd-supply-2 = <&buck123_reg>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]52 bootph-pre-ram;
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]53};
54
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]55&ospi0 {
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]56 /* Address change for data region (32-bit) */
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]57 reg = <0x0 0x47040000 0x0 0x100>,
58 <0x0 0x50000000 0x0 0x8000000>;
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]59};