Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 2 | /* |
Ryan Harkin | 0e5827f | 2013-04-09 02:20:31 +0000 | [diff] [blame] | 3 | * (C) Copyright 2011 ARM Limited |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 4 | * (C) Copyright 2010 Linaro |
| 5 | * Matt Waddel, <matt.waddel@linaro.org> |
| 6 | * |
| 7 | * Configuration for Versatile Express. Parts were derived from other ARM |
| 8 | * configurations. |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 9 | */ |
| 10 | |
Ryan Harkin | 0e5827f | 2013-04-09 02:20:31 +0000 | [diff] [blame] | 11 | #ifndef __VEXPRESS_COMMON_H |
| 12 | #define __VEXPRESS_COMMON_H |
| 13 | |
| 14 | /* |
| 15 | * Definitions copied from linux kernel: |
| 16 | * arch/arm/mach-vexpress/include/mach/motherboard.h |
| 17 | */ |
Kristian Amlie | 39fc095 | 2021-09-10 08:19:19 +0200 | [diff] [blame] | 18 | #ifdef VEXPRESS_ORIGINAL_MEMORY_MAP |
Ryan Harkin | 0e5827f | 2013-04-09 02:20:31 +0000 | [diff] [blame] | 19 | /* CS register bases for the original memory map. */ |
| 20 | #define V2M_PA_CS0 0x40000000 |
| 21 | #define V2M_PA_CS1 0x44000000 |
| 22 | #define V2M_PA_CS2 0x48000000 |
| 23 | #define V2M_PA_CS3 0x4c000000 |
| 24 | #define V2M_PA_CS7 0x10000000 |
| 25 | |
| 26 | #define V2M_PERIPH_OFFSET(x) (x << 12) |
| 27 | #define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(0)) |
| 28 | #define V2M_SYSCTL (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1)) |
| 29 | #define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2)) |
| 30 | |
| 31 | #define V2M_BASE 0x60000000 |
Ryan Harkin | 0e5827f | 2013-04-09 02:20:31 +0000 | [diff] [blame] | 32 | #elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP) |
| 33 | /* CS register bases for the extended memory map. */ |
| 34 | #define V2M_PA_CS0 0x08000000 |
| 35 | #define V2M_PA_CS1 0x0c000000 |
| 36 | #define V2M_PA_CS2 0x14000000 |
| 37 | #define V2M_PA_CS3 0x18000000 |
| 38 | #define V2M_PA_CS7 0x1c000000 |
| 39 | |
| 40 | #define V2M_PERIPH_OFFSET(x) (x << 16) |
| 41 | #define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1)) |
| 42 | #define V2M_SYSCTL (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2)) |
| 43 | #define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(3)) |
| 44 | |
| 45 | #define V2M_BASE 0x80000000 |
Ryan Harkin | 0e5827f | 2013-04-09 02:20:31 +0000 | [diff] [blame] | 46 | #endif |
| 47 | |
| 48 | /* |
| 49 | * Physical addresses, offset from V2M_PA_CS0-3 |
| 50 | */ |
| 51 | #define V2M_NOR0 (V2M_PA_CS0) |
| 52 | #define V2M_NOR1 (V2M_PA_CS1) |
| 53 | #define V2M_SRAM (V2M_PA_CS2) |
| 54 | #define V2M_VIDEO_SRAM (V2M_PA_CS3 + 0x00000000) |
Ryan Harkin | 0e5827f | 2013-04-09 02:20:31 +0000 | [diff] [blame] | 55 | #define V2M_ISP1761 (V2M_PA_CS3 + 0x03000000) |
| 56 | |
| 57 | /* Common peripherals relative to CS7. */ |
| 58 | #define V2M_AACI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(4)) |
Ryan Harkin | 0e5827f | 2013-04-09 02:20:31 +0000 | [diff] [blame] | 59 | #define V2M_KMI0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(6)) |
| 60 | #define V2M_KMI1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(7)) |
| 61 | |
| 62 | #define V2M_UART0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(9)) |
| 63 | #define V2M_UART1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(10)) |
| 64 | #define V2M_UART2 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(11)) |
| 65 | #define V2M_UART3 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(12)) |
| 66 | |
| 67 | #define V2M_WDT (V2M_PA_CS7 + V2M_PERIPH_OFFSET(15)) |
| 68 | |
| 69 | #define V2M_TIMER01 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(17)) |
| 70 | #define V2M_TIMER23 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(18)) |
| 71 | |
| 72 | #define V2M_SERIAL_BUS_DVI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(22)) |
| 73 | #define V2M_RTC (V2M_PA_CS7 + V2M_PERIPH_OFFSET(23)) |
| 74 | |
| 75 | #define V2M_CF (V2M_PA_CS7 + V2M_PERIPH_OFFSET(26)) |
| 76 | |
| 77 | #define V2M_CLCD (V2M_PA_CS7 + V2M_PERIPH_OFFSET(31)) |
| 78 | #define V2M_SIZE_CS7 V2M_PERIPH_OFFSET(32) |
| 79 | |
| 80 | /* System register offsets. */ |
| 81 | #define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) |
| 82 | #define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) |
| 83 | #define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) |
| 84 | |
| 85 | /* |
| 86 | * Configuration |
| 87 | */ |
| 88 | #define SYS_CFG_START (1 << 31) |
| 89 | #define SYS_CFG_WRITE (1 << 30) |
| 90 | #define SYS_CFG_OSC (1 << 20) |
| 91 | #define SYS_CFG_VOLT (2 << 20) |
| 92 | #define SYS_CFG_AMP (3 << 20) |
| 93 | #define SYS_CFG_TEMP (4 << 20) |
| 94 | #define SYS_CFG_RESET (5 << 20) |
| 95 | #define SYS_CFG_SCC (6 << 20) |
| 96 | #define SYS_CFG_MUXFPGA (7 << 20) |
| 97 | #define SYS_CFG_SHUTDOWN (8 << 20) |
| 98 | #define SYS_CFG_REBOOT (9 << 20) |
| 99 | #define SYS_CFG_DVIMODE (11 << 20) |
| 100 | #define SYS_CFG_POWER (12 << 20) |
| 101 | #define SYS_CFG_SITE_MB (0 << 16) |
| 102 | #define SYS_CFG_SITE_DB1 (1 << 16) |
| 103 | #define SYS_CFG_SITE_DB2 (2 << 16) |
| 104 | #define SYS_CFG_STACK(n) ((n) << 12) |
| 105 | |
| 106 | #define SYS_CFG_ERR (1 << 1) |
| 107 | #define SYS_CFG_COMPLETE (1 << 0) |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 108 | |
| 109 | /* Board info register */ |
Ryan Harkin | 0e5827f | 2013-04-09 02:20:31 +0000 | [diff] [blame] | 110 | #define SYS_ID V2M_SYSREGS |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 111 | |
Ryan Harkin | 0e5827f | 2013-04-09 02:20:31 +0000 | [diff] [blame] | 112 | #define SCTL_BASE V2M_SYSCTL |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 113 | #define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0) |
| 114 | |
Rob Herring | 9560ec4 | 2013-10-04 10:22:45 -0500 | [diff] [blame] | 115 | #define CONFIG_SYS_TIMER_RATE 1000000 |
Ian Campbell | 5be3257 | 2013-11-17 15:17:42 +0000 | [diff] [blame] | 116 | #define CONFIG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4) |
Rob Herring | 9560ec4 | 2013-10-04 10:22:45 -0500 | [diff] [blame] | 117 | #define CONFIG_SYS_TIMER_COUNTS_DOWN |
| 118 | |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 119 | /* PL011 Serial Configuration */ |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 120 | #define CONFIG_PL011_CLOCK 24000000 |
| 121 | #define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ |
| 122 | (void *)CONFIG_SYS_SERIAL1} |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 123 | |
Ryan Harkin | 0e5827f | 2013-04-09 02:20:31 +0000 | [diff] [blame] | 124 | #define CONFIG_SYS_SERIAL0 V2M_UART0 |
| 125 | #define CONFIG_SYS_SERIAL1 V2M_UART1 |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 126 | |
Matt Waddel | c5a6a40 | 2011-04-16 11:54:08 +0000 | [diff] [blame] | 127 | #define CONFIG_SYS_MMC_MAX_BLK_COUNT 127 |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 128 | |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 129 | /* Miscellaneous configurable options */ |
Ryan Harkin | 0e5827f | 2013-04-09 02:20:31 +0000 | [diff] [blame] | 130 | #define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000) |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 131 | |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 132 | /* Physical Memory Map */ |
Ryan Harkin | 0e5827f | 2013-04-09 02:20:31 +0000 | [diff] [blame] | 133 | #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ |
| 134 | #define PHYS_SDRAM_2 (((unsigned int)V2M_BASE) + \ |
| 135 | ((unsigned int)0x20000000)) |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 136 | #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ |
| 137 | #define PHYS_SDRAM_2_SIZE 0x20000000 /* 512 MB */ |
| 138 | |
| 139 | /* additions for new relocation code */ |
| 140 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 141 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 142 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 143 | CONFIG_SYS_INIT_RAM_SIZE - \ |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 144 | GENERATED_GBL_DATA_SIZE) |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 145 | #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET |
Dennis Gilmore | 803574a | 2015-06-28 14:05:12 -0500 | [diff] [blame] | 146 | |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 147 | /* Basic environment settings */ |
Dennis Gilmore | 803574a | 2015-06-28 14:05:12 -0500 | [diff] [blame] | 148 | #define BOOT_TARGET_DEVICES(func) \ |
| 149 | func(MMC, mmc, 1) \ |
| 150 | func(MMC, mmc, 0) \ |
| 151 | func(PXE, pxe, na) \ |
| 152 | func(DHCP, dhcp, na) |
| 153 | #include <config_distro_bootcmd.h> |
| 154 | |
Ryan Harkin | 0e5827f | 2013-04-09 02:20:31 +0000 | [diff] [blame] | 155 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Kristian Amlie | 8f8a299 | 2021-09-07 08:37:51 +0200 | [diff] [blame] | 156 | "kernel_addr_r=0x60100000\0" \ |
| 157 | "fdt_addr_r=0x60000000\0" \ |
| 158 | "bootargs=console=tty0 console=ttyAMA0,38400n8\0" \ |
Dennis Gilmore | 803574a | 2015-06-28 14:05:12 -0500 | [diff] [blame] | 159 | BOOTENV \ |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 160 | "console=ttyAMA0,38400n8\0" \ |
| 161 | "dram=1024M\0" \ |
| 162 | "root=/dev/sda1 rw\0" \ |
| 163 | "mtd=armflash:1M@0x800000(uboot),7M@0x1000000(kernel)," \ |
| 164 | "24M@0x2000000(initrd)\0" \ |
| 165 | "flashargs=setenv bootargs root=${root} console=${console} " \ |
| 166 | "mem=${dram} mtdparts=${mtd} mmci.fmax=190000 " \ |
| 167 | "devtmpfs.mount=0 vmalloc=256M\0" \ |
| 168 | "bootflash=run flashargs; " \ |
Jason Hobbs | 0c16168 | 2011-08-23 11:06:59 +0000 | [diff] [blame] | 169 | "cp ${ramdisk_addr} ${ramdisk_addr_r} ${maxramdisk}; " \ |
Kristian Amlie | ce0d27e | 2020-02-25 18:22:16 +0100 | [diff] [blame] | 170 | "bootm ${kernel_addr} ${ramdisk_addr_r}\0" \ |
| 171 | "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 172 | |
| 173 | /* FLASH and environment organization */ |
| 174 | #define PHYS_FLASH_SIZE 0x04000000 /* 64MB */ |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 175 | #define CONFIG_SYS_FLASH_SIZE 0x04000000 |
Ryan Harkin | 0e5827f | 2013-04-09 02:20:31 +0000 | [diff] [blame] | 176 | #define CONFIG_SYS_FLASH_BASE0 V2M_NOR0 |
| 177 | #define CONFIG_SYS_FLASH_BASE1 V2M_NOR1 |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 178 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE0 |
| 179 | |
| 180 | /* Timeout values in ticks */ |
| 181 | #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ |
| 182 | #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ |
| 183 | |
| 184 | /* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */ |
| 185 | #define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */ |
| 186 | #define FLASH_MAX_SECTOR_SIZE 0x00040000 /* 256 KB sectors */ |
| 187 | |
| 188 | /* Room required on the stack for the environment data */ |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 189 | |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 190 | /* |
| 191 | * Amount of flash used for environment: |
| 192 | * We don't know which end has the small erase blocks so we use the penultimate |
| 193 | * sector location for the environment |
| 194 | */ |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 195 | |
| 196 | /* Store environment at top of flash */ |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 197 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ |
| 198 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE0, \ |
| 199 | CONFIG_SYS_FLASH_BASE1 } |
| 200 | |
| 201 | /* Monitor Command Prompt */ |
| 202 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
Matt Waddel | 35c638b | 2010-10-07 15:48:45 -0600 | [diff] [blame] | 203 | |
Ryan Harkin | 0e5827f | 2013-04-09 02:20:31 +0000 | [diff] [blame] | 204 | #endif /* VEXPRESS_COMMON_H */ |