David Huang | 6109820 | 2022-01-25 20:56:31 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Configuration header file for K3 J721S2 EVM |
| 4 | * |
| 5 | * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ |
| 6 | * David Huang <d-huang@ti.com> |
| 7 | */ |
| 8 | |
| 9 | #ifndef __CONFIG_J721S2_EVM_H |
| 10 | #define __CONFIG_J721S2_EVM_H |
| 11 | |
| 12 | #include <linux/sizes.h> |
| 13 | #include <config_distro_bootcmd.h> |
| 14 | #include <environment/ti/mmc.h> |
| 15 | #include <environment/ti/k3_rproc.h> |
| 16 | #include <environment/ti/ufs.h> |
| 17 | #include <environment/ti/k3_dfu.h> |
| 18 | |
| 19 | /* DDR Configuration */ |
| 20 | #define CONFIG_SYS_SDRAM_BASE1 0x880000000 |
| 21 | |
| 22 | /* SPL Loader Configuration */ |
| 23 | #if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) |
| 24 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ |
| 25 | CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE) |
| 26 | #define CONFIG_SYS_UBOOT_BASE 0x50280000 |
| 27 | /* Image load address in RAM for DFU boot*/ |
| 28 | #else |
| 29 | #define CONFIG_SYS_UBOOT_BASE 0x50080000 |
| 30 | /* |
| 31 | * Maximum size in memory allocated to the SPL BSS. Keep it as tight as |
| 32 | * possible (to allow the build to go through), as this directly affects |
| 33 | * our memory footprint. The less we use for BSS the more we have available |
| 34 | * for everything else. |
| 35 | */ |
| 36 | #define CONFIG_SPL_BSS_MAX_SIZE 0xA000 |
| 37 | /* |
| 38 | * Link BSS to be within SPL in a dedicated region located near the top of |
| 39 | * the MCU SRAM, this way making it available also before relocation. Note |
| 40 | * that we are not using the actual top of the MCU SRAM as there is a memory |
| 41 | * location filled in by the boot ROM that we want to read out without any |
| 42 | * interference from the C context. |
| 43 | */ |
| 44 | #define CONFIG_SPL_BSS_START_ADDR (0x41c80000 -\ |
| 45 | CONFIG_SPL_BSS_MAX_SIZE) |
| 46 | /* Set the stack right below the SPL BSS section */ |
| 47 | #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR |
| 48 | /* Configure R5 SPL post-relocation malloc pool in DDR */ |
| 49 | #define CONFIG_SYS_SPL_MALLOC_START 0x84000000 |
| 50 | #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M |
| 51 | /* Image load address in RAM for DFU boot*/ |
| 52 | #endif |
| 53 | |
| 54 | #ifdef CONFIG_SYS_K3_SPL_ATF |
| 55 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" |
| 56 | #endif |
| 57 | |
| 58 | #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE |
| 59 | |
| 60 | #define CONFIG_SYS_BOOTM_LEN SZ_64M |
| 61 | #define CONFIG_CQSPI_REF_CLK 133333333 |
| 62 | |
| 63 | /* HyperFlash related configuration */ |
| 64 | #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 |
| 65 | |
| 66 | /* U-Boot general configuration */ |
| 67 | #define EXTRA_ENV_J721S2_BOARD_SETTINGS \ |
| 68 | "default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ |
| 69 | "findfdt=" \ |
| 70 | "setenv name_fdt ${default_device_tree};" \ |
| 71 | "setenv fdtfile ${name_fdt}\0" \ |
| 72 | "name_kern=Image\0" \ |
| 73 | "console=ttyS2,115200n8\0" \ |
| 74 | "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02880000 " \ |
| 75 | "${mtdparts}\0" \ |
| 76 | "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0" |
| 77 | |
| 78 | #define PARTS_DEFAULT \ |
| 79 | /* Linux partitions */ \ |
| 80 | "uuid_disk=${uuid_gpt_disk};" \ |
| 81 | "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" |
| 82 | |
| 83 | #ifdef CONFIG_SYS_K3_SPL_ATF |
| 84 | #if defined(CONFIG_TARGET_J721S2_R5_EVM) |
| 85 | #define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC \ |
| 86 | "addr_mcur5f0_0load=0x89000000\0" \ |
| 87 | "name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw\0" |
| 88 | #elif defined(CONFIG_TARGET_J7200_R5_EVM) |
| 89 | #define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC \ |
| 90 | "addr_mcur5f0_0load=0x89000000\0" \ |
| 91 | "name_mcur5f0_0fw=/lib/firmware/j7200-mcu-r5f0_0-fw\0" |
| 92 | #endif /* CONFIG_TARGET_J721S2_R5_EVM */ |
| 93 | #else |
| 94 | #define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC "" |
| 95 | #endif /* CONFIG_SYS_K3_SPL_ATF */ |
| 96 | |
| 97 | /* U-Boot MMC-specific configuration */ |
| 98 | #define EXTRA_ENV_J721S2_BOARD_SETTINGS_MMC \ |
| 99 | "boot=mmc\0" \ |
| 100 | "mmcdev=1\0" \ |
| 101 | "bootpart=1:2\0" \ |
| 102 | "bootdir=/boot\0" \ |
| 103 | EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC \ |
| 104 | "rd_spec=-\0" \ |
| 105 | "init_mmc=run args_all args_mmc\0" \ |
| 106 | "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \ |
| 107 | "get_overlay_mmc=" \ |
| 108 | "fdt address ${fdtaddr};" \ |
| 109 | "fdt resize 0x100000;" \ |
| 110 | "for overlay in $name_overlays;" \ |
| 111 | "do;" \ |
| 112 | "load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && " \ |
| 113 | "fdt apply ${dtboaddr};" \ |
| 114 | "done;\0" \ |
| 115 | "partitions=" PARTS_DEFAULT \ |
| 116 | "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \ |
| 117 | "${bootdir}/${name_kern}\0" \ |
| 118 | "get_fit_mmc=load mmc ${bootpart} ${addr_fit} " \ |
| 119 | "${bootdir}/${name_fit}\0" \ |
| 120 | "partitions=" PARTS_DEFAULT |
| 121 | |
| 122 | /* Set the default list of remote processors to boot */ |
| 123 | #if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) |
| 124 | #ifdef DEFAULT_RPROCS |
| 125 | #undef DEFAULT_RPROCS |
| 126 | #endif |
| 127 | #endif |
| 128 | |
| 129 | #ifdef CONFIG_TARGET_J721S2_A72_EVM |
| 130 | #define DEFAULT_RPROCS "" \ |
| 131 | "2 /lib/firmware/j721s2-main-r5f0_0-fw " \ |
| 132 | "3 /lib/firmware/j721s2-main-r5f0_1-fw " \ |
| 133 | "4 /lib/firmware/j721s2-main-r5f1_0-fw " \ |
| 134 | "5 /lib/firmware/j721s2-main-r5f1_1-fw " \ |
| 135 | "6 /lib/firmware/j721s2-c71_0-fw " \ |
| 136 | "7 /lib/firmware/j721s2-c71_1-fw " |
| 137 | #endif /* CONFIG_TARGET_J721S2_A72_EVM */ |
| 138 | |
| 139 | #ifdef CONFIG_TARGET_J7200_A72_EVM |
| 140 | #define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \ |
| 141 | "do_main_cpsw0_qsgmii_phyinit=1\0" \ |
| 142 | "init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;" \ |
| 143 | "gpio clear gpio@22_16\0" \ |
| 144 | "main_cpsw0_qsgmii_phyinit=" \ |
| 145 | "if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot} -eq 1 && " \ |
| 146 | "test ${boot} = mmc; then " \ |
| 147 | "run init_main_cpsw0_qsgmii_phy;" \ |
| 148 | "fi;\0" |
| 149 | #define DEFAULT_RPROCS "" \ |
| 150 | "2 /lib/firmware/j7200-main-r5f0_0-fw " \ |
| 151 | "3 /lib/firmware/j7200-main-r5f0_1-fw " |
| 152 | #endif /* CONFIG_TARGET_J7200_A72_EVM */ |
| 153 | |
| 154 | #ifndef EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY |
| 155 | #define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY |
| 156 | #endif |
| 157 | |
| 158 | /* set default dfu_bufsiz to 128KB (sector size of OSPI) */ |
| 159 | #define EXTRA_ENV_DFUARGS \ |
| 160 | DFU_ALT_INFO_MMC \ |
| 161 | DFU_ALT_INFO_EMMC \ |
| 162 | DFU_ALT_INFO_RAM \ |
| 163 | DFU_ALT_INFO_OSPI |
| 164 | |
| 165 | #if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) |
| 166 | #define EXTRA_ENV_J721S2_BOARD_SETTINGS_MTD \ |
| 167 | "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ |
| 168 | "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" |
| 169 | #else |
| 170 | #define EXTRA_ENV_J721S2_BOARD_SETTINGS_MTD |
| 171 | #endif |
| 172 | |
| 173 | /* Incorporate settings into the U-Boot environment */ |
| 174 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 175 | DEFAULT_LINUX_BOOT_ENV \ |
| 176 | DEFAULT_MMC_TI_ARGS \ |
| 177 | DEFAULT_FIT_TI_ARGS \ |
| 178 | EXTRA_ENV_J721S2_BOARD_SETTINGS \ |
| 179 | EXTRA_ENV_J721S2_BOARD_SETTINGS_MMC \ |
| 180 | EXTRA_ENV_RPROC_SETTINGS \ |
| 181 | EXTRA_ENV_DFUARGS \ |
| 182 | DEFAULT_UFS_TI_ARGS \ |
| 183 | EXTRA_ENV_J721S2_BOARD_SETTINGS_MTD \ |
| 184 | EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY |
| 185 | |
| 186 | /* Now for the remaining common defines */ |
| 187 | #include <configs/ti_armv7_common.h> |
| 188 | |
| 189 | /* MMC ENV related defines */ |
| 190 | |
| 191 | #endif /* __CONFIG_J721S2_EVM_H */ |