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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Simon Glass45be32c2014-12-10 08:55:51 -07002/*
3 * Test-related constants for sandbox
4 *
5 * Copyright (c) 2014 Google, Inc
Simon Glass45be32c2014-12-10 08:55:51 -07006 */
7
8#ifndef __ASM_TEST_H
9#define __ASM_TEST_H
10
Simon Glassc3b5adf2021-11-19 13:23:50 -070011#include <video.h>
12
Simon Glass45be32c2014-12-10 08:55:51 -070013/* The sandbox driver always permits an I2C device with this address */
Simon Glass70778bc2015-03-05 12:25:26 -070014#define SANDBOX_I2C_TEST_ADDR 0x59
15
16#define SANDBOX_PCI_VENDOR_ID 0x1234
Simon Glass21c8f1a2019-09-25 08:56:01 -060017#define SANDBOX_PCI_SWAP_CASE_EMUL_ID 0x5678
Simon Glass8c501022019-12-06 21:41:54 -070018#define SANDBOX_PCI_PMC_EMUL_ID 0x5677
Simon Glass937bb472019-12-06 21:41:57 -070019#define SANDBOX_PCI_P2SB_EMUL_ID 0x5676
Simon Glass70778bc2015-03-05 12:25:26 -070020#define SANDBOX_PCI_CLASS_CODE PCI_CLASS_CODE_COMM
21#define SANDBOX_PCI_CLASS_SUB_CODE PCI_CLASS_SUB_CODE_COMM_SERIAL
Simon Glass45be32c2014-12-10 08:55:51 -070022
Bin Mengd74d3122018-08-03 01:14:53 -070023#define PCI_CAP_ID_PM_OFFSET 0x50
24#define PCI_CAP_ID_EXP_OFFSET 0x60
25#define PCI_CAP_ID_MSIX_OFFSET 0x70
Alex Margineanf1274432019-06-07 11:24:24 +030026#define PCI_CAP_ID_EA_OFFSET 0x80
Bin Mengd74d3122018-08-03 01:14:53 -070027
28#define PCI_EXT_CAP_ID_ERR_OFFSET 0x100
29#define PCI_EXT_CAP_ID_VC_OFFSET 0x200
30#define PCI_EXT_CAP_ID_DSN_OFFSET 0x300
31
Bin Mengc69ae412018-08-03 01:14:46 -070032/* Useful for PCI_VDEVICE() macro */
33#define PCI_VENDOR_ID_SANDBOX SANDBOX_PCI_VENDOR_ID
34#define SWAP_CASE_DRV_DATA 0x55aa
35
Simon Glass8cc4d822015-07-06 12:54:24 -060036#define SANDBOX_CLK_RATE 32768
37
Alex Margineanf1274432019-06-07 11:24:24 +030038/* Macros used to test PCI EA capability structure */
39#define PCI_CAP_EA_BASE_LO0 0x00100000
40#define PCI_CAP_EA_BASE_LO1 0x00110000
41#define PCI_CAP_EA_BASE_LO2 0x00120000
42#define PCI_CAP_EA_BASE_LO4 0x00140000
43#define PCI_CAP_EA_BASE_HI2 0x00020000ULL
44#define PCI_CAP_EA_BASE_HI4 0x00040000ULL
45#define PCI_CAP_EA_SIZE_LO 0x0000ffff
46#define PCI_CAP_EA_SIZE_HI 0x00000010ULL
47#define PCI_EA_BAR2_MAGIC 0x72727272
48#define PCI_EA_BAR4_MAGIC 0x74747474
49
Simon Glassa847b272020-02-06 09:54:57 -070050enum {
51 SANDBOX_IRQN_PEND = 1, /* Interrupt number for 'pending' test */
52};
53
Simon Glasscd556522015-07-06 12:54:35 -060054/* System controller driver data */
55enum {
56 SYSCON0 = 32,
57 SYSCON1,
58
59 SYSCON_COUNT
60};
61
Simon Glass4c70ed92015-04-20 12:37:15 -060062/**
Simon Glass9b306e52021-01-16 14:52:22 -070063 */
64enum cros_ec_test_t {
65 CROSECT_BREAK_HELLO = BIT(1),
Simon Glass9d702522021-01-16 14:52:28 -070066 CROSECT_LID_OPEN = BIT(2),
Simon Glass9b306e52021-01-16 14:52:22 -070067};
68
69/**
Simon Glass4c70ed92015-04-20 12:37:15 -060070 * sandbox_i2c_set_test_mode() - set test mode for running unit tests
71 *
72 * See sandbox_i2c_xfer() for the behaviour changes.
73 *
74 * @bus: sandbox I2C bus to adjust
75 * @test_mode: true to select test mode, false to run normally
76 */
77void sandbox_i2c_set_test_mode(struct udevice *bus, bool test_mode);
78
Simon Glass45be32c2014-12-10 08:55:51 -070079enum sandbox_i2c_eeprom_test_mode {
80 SIE_TEST_MODE_NONE,
81 /* Permits read/write of only one byte per I2C transaction */
82 SIE_TEST_MODE_SINGLE_BYTE,
83};
84
85void sandbox_i2c_eeprom_set_test_mode(struct udevice *dev,
86 enum sandbox_i2c_eeprom_test_mode mode);
87
88void sandbox_i2c_eeprom_set_offset_len(struct udevice *dev, int offset_len);
89
Robert Beckettf695f6e2019-10-28 17:44:59 +000090void sandbox_i2c_eeprom_set_chip_addr_offset_mask(struct udevice *dev,
91 uint mask);
92
Robert Beckett1fe8a492019-10-28 17:44:58 +000093uint sanbox_i2c_eeprom_get_prev_addr(struct udevice *dev);
94
95uint sanbox_i2c_eeprom_get_prev_offset(struct udevice *dev);
96
Simon Glassc404aa62015-04-20 12:37:24 -060097/**
98 * sandbox_i2c_rtc_set_offset() - set the time offset from system/base time
99 *
100 * @dev: RTC device to adjust
101 * @use_system_time: true to use system time, false to use @base_time
102 * @offset: RTC offset from current system/base time (-1 for no
103 * change)
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100104 * Return: old value of RTC offset
Simon Glassc404aa62015-04-20 12:37:24 -0600105 */
106long sandbox_i2c_rtc_set_offset(struct udevice *dev, bool use_system_time,
107 int offset);
108
109/**
110 * sandbox_i2c_rtc_get_set_base_time() - get and set the base time
111 *
112 * @dev: RTC device to adjust
113 * @base_time: New base system time (set to -1 for no change)
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100114 * Return: old base time
Simon Glassc404aa62015-04-20 12:37:24 -0600115 */
116long sandbox_i2c_rtc_get_set_base_time(struct udevice *dev, long base_time);
117
Simon Glassbe4ebd12015-11-08 23:48:06 -0700118int sandbox_usb_keyb_add_string(struct udevice *dev, const char *str);
119
Mario Six02ad6fb2018-09-27 09:19:31 +0200120/**
121 * sandbox_osd_get_mem() - get the internal memory of a sandbox OSD
122 *
123 * @dev: OSD device for which to access the internal memory for
124 * @buf: pointer to buffer to receive the OSD memory data
125 * @buflen: length of buffer in bytes
126 */
127int sandbox_osd_get_mem(struct udevice *dev, u8 *buf, size_t buflen);
Simon Glass5620cf82018-10-01 12:22:40 -0600128
129/**
130 * sandbox_pwm_get_config() - get the PWM config for a channel
131 *
132 * @dev: Device to check
133 * @channel: Channel number to check
134 * @period_ns: Period of the PWM in nanoseconds
135 * @duty_ns: Current duty cycle of the PWM in nanoseconds
136 * @enable: true if the PWM is enabled
137 * @polarity: true if the PWM polarity is active high
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100138 * Return: 0 if OK, -ENOSPC if the PWM number is invalid
Simon Glass5620cf82018-10-01 12:22:40 -0600139 */
140int sandbox_pwm_get_config(struct udevice *dev, uint channel, uint *period_nsp,
141 uint *duty_nsp, bool *enablep, bool *polarityp);
142
Simon Glass36eee8c2018-11-06 15:21:41 -0700143/**
144 * sandbox_sf_set_block_protect() - Set the BP bits of the status register
145 *
146 * @dev: Device to update
147 * @bp_mask: BP bits to set (bits 2:0, so a value of 0 to 7)
148 */
149void sandbox_sf_set_block_protect(struct udevice *dev, int bp_mask);
150
Simon Glassed96cde2018-12-10 10:37:33 -0700151/**
152 * sandbox_get_codec_params() - Read back codec parameters
153 *
154 * This reads back the parameters set by audio_codec_set_params() for the
155 * sandbox audio driver. Arguments are as for that function.
156 */
157void sandbox_get_codec_params(struct udevice *dev, int *interfacep, int *ratep,
158 int *mclk_freqp, int *bits_per_samplep,
159 uint *channelsp);
160
Simon Glassc953aaf2018-12-10 10:37:34 -0700161/**
162 * sandbox_get_i2s_sum() - Read back the sum of the audio data so far
163 *
164 * This data is provided to the sandbox driver by the I2S tx_data() method.
165 *
166 * @dev: Device to check
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100167 * Return: sum of audio data
Simon Glassc953aaf2018-12-10 10:37:34 -0700168 */
169int sandbox_get_i2s_sum(struct udevice *dev);
170
Simon Glass76072ac2018-12-10 10:37:36 -0700171/**
172 * sandbox_get_setup_called() - Returns the number of times setup(*) was called
173 *
174 * This is used in the sound test
175 *
176 * @dev: Device to check
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100177 * Return: call count for the setup() method
Simon Glass76072ac2018-12-10 10:37:36 -0700178 */
179int sandbox_get_setup_called(struct udevice *dev);
180
181/**
Simon Glass70bc14b2020-02-03 07:36:06 -0700182 * sandbox_get_sound_active() - Returns whether sound play is in progress
183 *
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100184 * Return: true if active, false if not
Simon Glass70bc14b2020-02-03 07:36:06 -0700185 */
186int sandbox_get_sound_active(struct udevice *dev);
187
188/**
Simon Glass76072ac2018-12-10 10:37:36 -0700189 * sandbox_get_sound_sum() - Read back the sum of the sound data so far
190 *
191 * This data is provided to the sandbox driver by the sound play() method.
192 *
193 * @dev: Device to check
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100194 * Return: sum of audio data
Simon Glass76072ac2018-12-10 10:37:36 -0700195 */
196int sandbox_get_sound_sum(struct udevice *dev);
197
Simon Glass53a68b32019-02-16 20:24:50 -0700198/**
Simon Glassecd02e72019-02-16 20:24:54 -0700199 * sandbox_set_allow_beep() - Set whether the 'beep' interface is supported
200 *
201 * @dev: Device to update
202 * @allow: true to allow the start_beep() method, false to disallow it
203 */
204void sandbox_set_allow_beep(struct udevice *dev, bool allow);
205
206/**
207 * sandbox_get_beep_frequency() - Get the frequency of the current beep
208 *
209 * @dev: Device to check
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100210 * Return: frequency of beep, if there is an active beep, else 0
Simon Glassecd02e72019-02-16 20:24:54 -0700211 */
212int sandbox_get_beep_frequency(struct udevice *dev);
213
214/**
Ovidiu Panaita2c9d012020-12-14 19:06:49 +0200215 * sandbox_spi_get_speed() - Get current speed setting of a sandbox spi bus
216 *
217 * @dev: Device to check
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100218 * Return: current bus speed
Ovidiu Panaita2c9d012020-12-14 19:06:49 +0200219 */
220uint sandbox_spi_get_speed(struct udevice *dev);
221
222/**
223 * sandbox_spi_get_mode() - Get current mode setting of a sandbox spi bus
224 *
225 * @dev: Device to check
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100226 * Return: current mode
Ovidiu Panaita2c9d012020-12-14 19:06:49 +0200227 */
228uint sandbox_spi_get_mode(struct udevice *dev);
229
230/**
Simon Glass53a68b32019-02-16 20:24:50 -0700231 * sandbox_get_pch_spi_protect() - Get the PCI SPI protection status
232 *
233 * @dev: Device to check
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100234 * Return: 0 if not protected, 1 if protected
Simon Glass53a68b32019-02-16 20:24:50 -0700235 */
236int sandbox_get_pch_spi_protect(struct udevice *dev);
237
Ramon Friedafdb3422019-04-27 11:15:24 +0300238/**
239 * sandbox_get_pci_ep_irq_count() - Get the PCI EP IRQ count
240 *
241 * @dev: Device to check
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100242 * Return: irq count
Ramon Friedafdb3422019-04-27 11:15:24 +0300243 */
244int sandbox_get_pci_ep_irq_count(struct udevice *dev);
245
Simon Glass72231f72019-09-25 08:56:42 -0600246/**
247 * sandbox_pci_read_bar() - Read the BAR value for a read_config operation
248 *
249 * This is used in PCI emulators to read a base address reset. This has special
250 * rules because when the register is set to 0xffffffff it can be used to
251 * discover the type and size of the BAR.
252 *
253 * @barval: Current value of the BAR
254 * @type: Type of BAR (PCI_BASE_ADDRESS_SPACE_IO or
255 * PCI_BASE_ADDRESS_MEM_TYPE_32)
256 * @size: Size of BAR in bytes
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100257 * Return: BAR value to return from emulator
Simon Glass72231f72019-09-25 08:56:42 -0600258 */
259uint sandbox_pci_read_bar(u32 barval, int type, uint size);
260
Simon Glassc667fb02019-10-11 16:16:48 -0600261/**
262 * sandbox_set_enable_memio() - Enable readl/writel() for sandbox
263 *
264 * Normally these I/O functions do nothing with sandbox. Certain tests need them
265 * to work as for other architectures, so this function can be used to enable
266 * them.
267 *
268 * @enable: true to enable, false to disable
269 */
270void sandbox_set_enable_memio(bool enable);
271
Simon Glass9b306e52021-01-16 14:52:22 -0700272/**
273 * sandbox_cros_ec_set_test_flags() - Set behaviour for testing purposes
274 *
275 * @dev: Device to check
276 * @flags: Flags to control behaviour (CROSECT_...)
277 */
278void sandbox_cros_ec_set_test_flags(struct udevice *dev, uint flags);
279
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300280/**
281 * sandbox_cros_ec_get_pwm_duty() - Get EC PWM config for testing purposes
282 *
283 * @dev: Device to check
284 * @index: PWM channel index
285 * @duty: Current duty cycle in 0..EC_PWM_MAX_DUTY range.
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100286 * Return: 0 if OK, -ENOSPC if the PWM number is invalid
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300287 */
288int sandbox_cros_ec_get_pwm_duty(struct udevice *dev, uint index, uint *duty);
289
Simon Glassc3b5adf2021-11-19 13:23:50 -0700290/**
291 * sandbox_sdl_set_bpp() - Set the depth of the sandbox display
292 *
293 * The device must not be active when this function is called. It activiates it
294 * before returning.
295 *
296 * This updates the depth value and adjusts a few other settings accordingly.
297 * It must be called before the display is probed.
298 *
299 * @dev: Device to adjust
300 * @l2bpp: depth to set
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100301 * Return: 0 if the device was already active, other error if it fails to probe
Simon Glassc3b5adf2021-11-19 13:23:50 -0700302 * after the change
303 */
304int sandbox_sdl_set_bpp(struct udevice *dev, enum video_log2_bpp l2bpp);
305
Simon Glass45be32c2014-12-10 08:55:51 -0700306#endif